[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN106653677A - SOI wafer preparation method - Google Patents

SOI wafer preparation method Download PDF

Info

Publication number
CN106653677A
CN106653677A CN201610844379.3A CN201610844379A CN106653677A CN 106653677 A CN106653677 A CN 106653677A CN 201610844379 A CN201610844379 A CN 201610844379A CN 106653677 A CN106653677 A CN 106653677A
Authority
CN
China
Prior art keywords
silicon
film
piece
layer
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610844379.3A
Other languages
Chinese (zh)
Inventor
王文庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd
Original Assignee
Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd filed Critical Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd
Priority to CN201610844379.3A priority Critical patent/CN106653677A/en
Publication of CN106653677A publication Critical patent/CN106653677A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to the technical field of SOI wafer preparation, and especially relates to an SOI wafer preparation method. The method, which is designed by improving the existing stripping technology, comprises the following steps: (a) depositing amorphous silicon on a mono-crystalline Si film layer produced by stripping, and carrying out heating at the temperature of 800-1000 DEG C; (b) oxidizing the silicon surface produced in step (a) to form a silicon oxide layer, and removing the silicon oxide layer with hydrofluoric acid; and (c) putting an SOI wafer obtained in step (b) into a sealed reaction chamber, pumping in H2 and anhydrous HCl gas in turn, pumping in N2 for a period of time, and taking out the SOI wafer. The mono-crystalline Si film on the top layer of the SOI wafer prepared by the method is of uniform thickness, low surface roughness and good quality.

Description

A kind of preparation method of SOI pieces
Technical field：
The present invention relates to the preparing technical field of SOI wafer, more particularly to a kind of preparation method of SOI pieces.
Background technology
SOI materials are described as the basis of " 21st century silicon integrated circuit technology ", and he can eliminate or mitigate body silicon In bulk effect, ghost effect and small-size effect etc., the fields such as super large-scale integration, photoelectron have it is wide should Use prospect.
The technology of preparing of SOI materials includes after all two kinds, i.e., the injection oxygen isolation technology with ion implanting as representative And bonding techniques (Bond) (SIMOX).Bonding techniques include traditional Bond and Etch back (BESOI) technologies and France One of SOITEC companies founder M.Bmel proposes binding hydrogen ions injection and the note hydrogen smart cut technique (Smart- being bonded Cut)。
But SIMOX technologies need to note O+Special implanter carries out the O of high dose+Ion implanting and prolonged high annealing It is (being more than or equal to 1300 DEG C), expensive, and top layer Si film and buried regions SiO2Quality still not as body single crystalline Si and thermally grown SiO2.The back side of BESOI technologies it is uniform it is thinning be a difficulty technique, it is uniform thinning below 1 μm of top layer Si film thickness Process complications will be made and its quality will be affected.
Smart peeling method is a kind of new technology that SIMOX technologies and BESOI technologies combine, there are both and Their deficiency is overcome, is a kind of ideal SOI technologies of preparing, comparable to be readily derived film thickness uniformity high The SOI wafer piece of soi layer, but, there is the damage layer caused because of ion implanting, surface in the soi wafer surface after stripping Coarse phenomenon can become bigger than the minute surface of common silicon chip, therefore, after ion implanting is peeled off, need to remove this kind of damage layer, table The coarse phenomenon in face.
In order to remove the damage layer etc., in finishing operation of the prior art after heat treatment is combined, often carry out being referred to as connecing Touch the mechanical polishing of polishing.If however, to fit wafer film (soi layer) implement comprising machining factor grinding, Because the allowance for grinding is uneven in face, therefore produce by the injection of hydrogen ion etc., the film peeling off and realize The problem that film thickness uniformity can deteriorate.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art part, there is provided a kind of preparation method of SOI pieces, intelligence is improved Energy lift-off technology, solves the shaggy problem of SOI pieces after ion implanting is peeled off.
For achieving the above object, the technical solution used in the present invention is：
A kind of preparation method of SOI pieces, it is at least a piece of in two panels monocrystalline silicon piece on form oxide-film, from wherein a piece of list The surface of the bonded wafers that crystal silicon chip is constituted injects hydrogen ion or noble gas ion to form ion implanted layer, then this is engaged The surface that the ion implanting of wafer is crossed is bonded with the substrate wafer surface being made up of another monocrystalline silicon piece by oxide-film, then Stripping heat treatment is carried out, peels off bonded wafers in the ion implanted layer, it is last further to apply heat treatment, it is securely joined with Two panels monocrystalline silicon piece, makes the top layer single crystalline Si thin-film surface planarization that stripping is produced, and comprises the steps：
(a) deposited amorphous silicon on the top layer single crystalline Si film layer for producing is peeled off, then in 800 DEG C～1000 DEG C of temperature Lower heating, makes non-crystalline silicon change into monocrystalline silicon, and together with top layer single crystalline Si film layer Si coatings are become；
B Si cover surfaces that () oxidation step (a) is produced form silicon oxide layer, and then hydrofluoric acid removes silicon oxide layer；
C step (b) gained SOI pieces are loaded enclosed reaction chamber by (), H is passed through successively2Top layer list is etched with anhydrous NCI gas Brilliant Si film layers, are finally passed through a period of time N2Afterwards, SOI pieces are taken out.
Preferably, at least a piece of surface implements after plasma treatment, to carry out by the oxide-film in two panels monocrystalline silicon piece Bonding.
Preferably, step (a) deposited amorphous silicon adopts Low Pressure Chemical Vapor Deposition.
Preferably, step (b) oxidation is realized by thermal oxide.
Preferably, 900 DEG C～1000 DEG C of step (b) oxidate temperature.
Preferably, the purity of the logical anhydrous NCI gas of step (c)>99.999%, 800 DEG C～1000 DEG C of etching temperature, the time 1min～1.5min.
Compared with prior art, the present invention has advantages below：
(1) it is provided without mechanical means and removes damage layer, the top layer monocrystalline for make the injection by hydrogen ion etc., peeling off and realizing The film thickness uniformity of Si films is guaranteed；
(2) using Si is first deposited, the rough surface for burying top layer single crystalline Si film after ion implanting is peeled off is filled and led up, by oxygen Change to be processed with oxide layer and remove former rough surface portion, tentatively reduce surface roughness, then through anhydrous HCl etchings, enter one Step reduces surface roughness；
(3) additionally, (a), (b), (c) three step have 800 DEG C～1000 DEG C of heating, can further plus strong bonding reduce The defect that ion implanting causes, improves SOI tablet qualities.
Specific embodiment
In order to be better understood from the present invention, below by embodiment, the present invention is further described, and embodiment is served only for solution The present invention is released, any restriction will not be constituted to the present invention.
Embodiment 1
2 10.16cm p-types (100) monocrystalline silicon pieces are taken, conventional cleaning takes wherein a piece of monocrystalline silicon piece brilliant as engagement Circle, being put into after cleaning in oxidation furnace carries out thermal oxide, in the thick SiO of its Surface Creation about 900nm2；
At room temperature bonded wafers are carried out with hydrogen ion injection, implantation dosage is 5 × 1016cm2, Implantation Energy is 190keV；2 silicon chips are carried out with oxygen plasma activation process to process with hydrophily, 300 DEG C after drying, low temperature is direct within 10 hours Bonding；
Be bonded 2 silicon chips are put into high-temperature annealing furnace carries out 550 DEG C of heat treatments, peels off with reference to wafer silicon chip, SiO is left on substrate wafer2Layer and top layer single crystalline Si film layer, form soi structure；
The Low Pressure Chemical Vapor Deposition on the top layer single crystalline Si film layer for producing is peeled off, at 560 DEG C and 100mTorr Under pressure, by the amorphous silicon layer of SiH4 gas aggradation 100nm, then heat at a temperature of 900 DEG C, non-crystalline silicon changes into list Crystal silicon, together with top layer single crystalline Si film layer Si coatings are become；
1000 DEG C carry out thermal oxide about 200nmSiO2 in oxidation furnace, and then hydrofluoric acid removes silicon oxide layer；
Gained SOI pieces are dried, load enclosed reaction chamber, the H of 30s purity >=99.999999% is passed through at 1000 DEG C2Go Except there may be silicon chip surface thin oxide layer, then it is passed through purity>99.999% anhydrous NCI gas, 800 DEG C of temperature, time 1.5min, etches Si film layers, is finally passed through a period of time N2, after removing the impurity and remnants HCl in reative cell, natural cooling To room temperature, SOI pieces are taken out.
The present embodiment single crystalline Si roughness of film rms value 0.18nm Jing after said method process, thickness evenness ± 3%.
Embodiment 2
2 10.16cm p-types (100) monocrystalline silicon pieces are taken, conventional cleaning takes wherein a piece of monocrystalline silicon piece brilliant as engagement Circle, being put into after cleaning in oxidation furnace carries out thermal oxide, in the thick SiO of its Surface Creation about 900nm2；
At room temperature bonded wafers are carried out with hydrogen ion injection, implantation dosage is 5 × 1016cm2, Implantation Energy is 190keV；2 silicon chips are carried out with oxygen plasma activation process to process with hydrophily, 300 DEG C after drying, low temperature is direct within 10 hours Bonding；
Be bonded 2 silicon chips are put into high-temperature annealing furnace carries out 550 DEG C of heat treatments, peels off with reference to wafer silicon chip, SiO is left on substrate wafer2Layer and top layer single crystalline Si film layer, form soi structure；
The Low Pressure Chemical Vapor Deposition on the top layer single crystalline Si film layer for producing is peeled off, at 560 DEG C and 100mTorr Under pressure, by the amorphous silicon layer of SiH4 gas aggradation 100nm, then heat at a temperature of 850 DEG C, non-crystalline silicon changes into list Crystal silicon, together with top layer single crystalline Si film layer Si coatings are become；
900 DEG C carry out thermal oxide about 150nmSiO2 in oxidation furnace, and then hydrofluoric acid removes silicon oxide layer；
Gained SOI pieces are dried, load enclosed reaction chamber, the H of 30s purity >=99.999999% is passed through at 1000 DEG C2Go Except there may be silicon chip surface thin oxide layer, then it is passed through purity>99.999% anhydrous NCI gas, 1000 DEG C of temperature, time 1min, etches Si film layers, is finally passed through a period of time N2, after removing the impurity and remnants HCl in reative cell, naturally cool to Room temperature, takes out SOI pieces.
The present embodiment single crystalline Si roughness of film rms value 0.21nm Jing after said method process, thickness evenness ± 3%.
Embodiment 3
2 10.16cm p-types (100) monocrystalline silicon pieces are taken, conventional cleaning takes wherein a piece of monocrystalline silicon piece brilliant as engagement Circle, being put into after cleaning in oxidation furnace carries out thermal oxide, in the thick SiO of its Surface Creation about 900nm2；
At room temperature bonded wafers are carried out with hydrogen ion injection, implantation dosage is 5 × 1016cm2, Implantation Energy is 190keV；2 silicon chips are carried out with oxygen plasma activation process to process with hydrophily, 300 DEG C after drying, low temperature is direct within 10 hours Bonding；
Be bonded 2 silicon chips are put into high-temperature annealing furnace carries out 550 DEG C of heat treatments, peels off with reference to wafer silicon chip, SiO is left on substrate wafer2Layer and top layer single crystalline Si film layer, form soi structure；
The Low Pressure Chemical Vapor Deposition on the top layer single crystalline Si film layer for producing is peeled off, at 560 DEG C and 100mTorr Under pressure, by the amorphous silicon layer of SiH4 gas aggradation 100nm, then heat at a temperature of 950 DEG C, non-crystalline silicon changes into list Crystal silicon, together with top layer single crystalline Si film layer Si coatings are become；
1000 DEG C carry out thermal oxide about 200nmSiO2 in oxidation furnace, and then hydrofluoric acid removes silicon oxide layer；
Gained SOI pieces are dried, load enclosed reaction chamber, the H of 30s purity >=99.999999% is passed through at 1000 DEG C2Go Except there may be silicon chip surface thin oxide layer, then it is passed through purity>99.999% anhydrous NCI gas, 950 DEG C of temperature, time 1.5min, etches Si film layers, is finally passed through a period of time N2, after removing the impurity and remnants HCl in reative cell, natural cooling To room temperature, SOI pieces are taken out.
The present embodiment single crystalline Si roughness of film rms value 0.17nm Jing after said method process, thickness evenness ± 3%.

Claims (6)

1. a kind of preparation method of SOI pieces, it is at least a piece of in two panels monocrystalline silicon piece on form oxide-film, from wherein a piece of monocrystalline The surface of the bonded wafers that silicon chip is constituted injects hydrogen ion or noble gas ion to form ion implanted layer, then the engagement is brilliant The surface that round ion implanting is crossed is bonded with the substrate wafer surface being made up of another monocrystalline silicon piece by oxide-film, Ran Houjin Row peels off heat treatment, peels off bonded wafers in the ion implanted layer, last further to apply heat treatment, is securely joined with two Piece monocrystalline silicon piece, makes the top layer single crystalline Si thin-film surface planarization that stripping is produced, it is characterised in that comprise the steps：
A () deposited amorphous silicon on the top layer single crystalline Si film layer for producing is peeled off, then adds at a temperature of 800 DEG C～1000 DEG C Heat, makes non-crystalline silicon change into monocrystalline silicon, and together with top layer single crystalline Si film layer Si coatings are become；
B Si cover surfaces that () oxidation step (a) is produced form silicon oxide layer, and then hydrofluoric acid removes silicon oxide layer；
C step (b) gained SOI pieces are loaded enclosed reaction chamber by (), H is passed through successively2Top layer single crystalline Si is etched with anhydrous NCI gas Film layer, is finally passed through a period of time N2Afterwards, SOI pieces are taken out.
2. the preparation method of SOI pieces according to claim 1, it is characterised in that：At least a piece of table in two panels monocrystalline silicon piece Face is implemented after plasma treatment, is bonded by the oxide-film.
3. the preparation method of SOI pieces according to claim 1, it is characterised in that：Step (a) deposited amorphous silicon adopts low pressure Chemical vapour deposition technique.
4. the preparation method of SOI pieces according to claim 1, it is characterised in that：Step (b) oxidation is realized by thermal oxide.
5. the preparation method of SOI pieces according to claim 4, it is characterised in that：900 DEG C of step (b) oxidate temperature～ 1000℃。
6. the preparation method of SOI pieces according to claim 1, it is characterised in that：Step (c) leads to the pure of anhydrous NCI gas Degree>99.999%, 800 DEG C～1000 DEG C of etching temperature, time 1min～1.5min.
CN201610844379.3A 2016-09-22 2016-09-22 SOI wafer preparation method Pending CN106653677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610844379.3A CN106653677A (en) 2016-09-22 2016-09-22 SOI wafer preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610844379.3A CN106653677A (en) 2016-09-22 2016-09-22 SOI wafer preparation method

Publications (1)

Publication Number Publication Date
CN106653677A true CN106653677A (en) 2017-05-10

Family

ID=58853251

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610844379.3A Pending CN106653677A (en) 2016-09-22 2016-09-22 SOI wafer preparation method

Country Status (1)

Country Link
CN (1) CN106653677A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729195A (en) * 2019-10-28 2020-01-24 沈阳硅基科技有限公司 Method for manufacturing planar transistor
CN111128784A (en) * 2019-12-31 2020-05-08 杭州中欣晶圆半导体股份有限公司 Method for measuring compactness of silicon dioxide film
CN116845027A (en) * 2023-09-01 2023-10-03 青禾晶元(天津)半导体材料有限公司 Preparation method of FD-SOI substrate and SOI device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832160A (en) * 2012-07-24 2012-12-19 沈阳硅基科技有限公司 Preparation method of SOI (silicon on insulator) silicon wafer
CN103700593A (en) * 2013-12-18 2014-04-02 北京大学 Method for preparing quasi-SOI (silicon on insulator) source drain multi-gate device
CN104115255A (en) * 2012-01-24 2014-10-22 信越半导体株式会社 Bonded SOI wafer manufacturing method
CN104810245A (en) * 2014-01-29 2015-07-29 北大方正集团有限公司 Method for improving groove morphology

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104115255A (en) * 2012-01-24 2014-10-22 信越半导体株式会社 Bonded SOI wafer manufacturing method
CN102832160A (en) * 2012-07-24 2012-12-19 沈阳硅基科技有限公司 Preparation method of SOI (silicon on insulator) silicon wafer
CN103700593A (en) * 2013-12-18 2014-04-02 北京大学 Method for preparing quasi-SOI (silicon on insulator) source drain multi-gate device
CN104810245A (en) * 2014-01-29 2015-07-29 北大方正集团有限公司 Method for improving groove morphology

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729195A (en) * 2019-10-28 2020-01-24 沈阳硅基科技有限公司 Method for manufacturing planar transistor
CN111128784A (en) * 2019-12-31 2020-05-08 杭州中欣晶圆半导体股份有限公司 Method for measuring compactness of silicon dioxide film
CN111128784B (en) * 2019-12-31 2022-06-24 杭州中欣晶圆半导体股份有限公司 Method for measuring compactness of silicon dioxide film
CN116845027A (en) * 2023-09-01 2023-10-03 青禾晶元(天津)半导体材料有限公司 Preparation method of FD-SOI substrate and SOI device
CN116845027B (en) * 2023-09-01 2023-11-21 青禾晶元(天津)半导体材料有限公司 Preparation method of FD-SOI substrate and SOI device

Similar Documents

Publication Publication Date Title
CN100446182C (en) A method of fabricating a composite substrate with improved electrical properties
KR100958467B1 (en) Method for reducing roughness of a thick insulating layer
US7521334B2 (en) Method for producing direct bonded wafer and direct bonded wafer
US8021910B2 (en) Method for producing single crystal silicon solar cell and single crystal silicon solar cell
US10829868B2 (en) Manufacturing method of SiC composite substrate
JPH11307747A (en) Soi substrate and production thereof
JPH11233449A (en) Manufacture of semiconductor substrate
US10431460B2 (en) Method for producing SiC composite substrate
EP2525390B1 (en) Method for producing bonded wafer
CN101188190B (en) SOQ substrate and method of manufacturing SOQ substrate
CN106653677A (en) SOI wafer preparation method
EP2953153B1 (en) Production method of soi wafer, and soi wafer
CN102832160B (en) Preparation method of SOI (silicon on insulator) silicon wafer
JP2003224247A (en) Soi wafer and its manufacturing method
US20080268621A1 (en) Method for manufacturing compound material wafer and corresponding compound material wafer
JP2013508962A (en) Method for producing a multilayer film comprising at least one ultrathin layer of crystalline silicon and device obtained by said method
CN113193109A (en) Preparation method of composite film and composite film
JP4581348B2 (en) Method for manufacturing bonded wafer and SOI wafer
CN116669523A (en) Preparation method of pyroelectric composite film
CN107785304B (en) SOI material with nitride film as insulating buried layer and preparation method thereof
CN116013845A (en) Preparation method of germanium structure substrate on insulating silicon
CN109055896A (en) A method of directly preparing graphene on an insulating substrate
CN110085509B (en) Preparation method of uniform thick film SOI (silicon on insulator) silicon chip
CN106992141B (en) Method for preparing SOI silicon chip with super-thick buried oxide layer
CN115775734A (en) SIC VDMOS device and method for improving yield and reliability of SIC device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170510

RJ01 Rejection of invention patent application after publication