CN106601748A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN106601748A CN106601748A CN201510660945.0A CN201510660945A CN106601748A CN 106601748 A CN106601748 A CN 106601748A CN 201510660945 A CN201510660945 A CN 201510660945A CN 106601748 A CN106601748 A CN 106601748A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- semiconductor device
- active area
- oxidation layer
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 108
- 230000003647 oxidation Effects 0.000 claims abstract description 55
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 55
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000007667 floating Methods 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 56
- 238000002347 injection Methods 0.000 claims description 42
- 239000007924 injection Substances 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000008859 change Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 239000007853 buffer solution Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000001010 compromised effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009036 growth inhibition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000036647 reaction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
The invention, which relates to the technical field of the semiconductor, provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: a patterning hard mask is formed on a semiconductor substrate and the semiconductor substrate is etched by using the hard mask to form a trench for accommodating a shallow trench isolation unit; a shallow trench isolation unit is formed in the trench; the hard mask is removed, nitrogen implantation is carried out on the semiconductor substrate corresponding to an active region, and thus a nitrogen implantation zone is formed in the semiconductor substrate, wherein the nitrogen concentration of the nitrogen implantation region at the edge of the active region is lower than that of the nitrogen implantation region at the center of the active region; a tunnel oxidation layer is formed on the semiconductor substrate in the active region, wherein the part, located at the edge of the active region, of the tunnel oxidation layer is thicker than the part, located at the center of the active region, of the tunnel oxidation layer; and a floating gate is formed on the tunnel oxidation layer. With the manufacturing method provided by the invention, the stress reading and disturb erasing performances of the Flash can be improved under the circumstance that the programming and erasing efficiency of the Flash are guaranteed.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and its
Manufacture method.
Background technology
In technical field of semiconductors, flash memory (Flash) device due to its own advantage and
It is widely used.In flush memory device especially p-Flash, in circulation behaviour repeatedly
Under work, once infringement occurs in tunnel oxidation layer (tunnel oxide), the electric charge for storing will be caused
Enhancement mode be lost in, ultimately result in erasing or write interference (erase/read disturb).
A kind of typical structure of existing semiconductor device including flash memory as shown in figure 1, including
Semiconductor substrate 100, the tunnel oxidation layer 101 in Semiconductor substrate 100, floating boom 102,
Dielectric layer 103 and control gate 104 between grid.Wherein, tunnel oxidation layer 101 is located at active area (AA)
The thickness of the part 1011 of marginal area is generally located at active district center than tunnel oxidation layer 101
The thickness of thin of the part in region；And tunnel oxidation layer 101 is located at the part in active-surface region
1011 is the part of the most fragile of tunnel oxidation layer 101, it is easy to infringement occur, so as to cause
The loss of the electric charge of storage, ultimately causes erasing or writes interference (erase/read disturb).
To solve the above problems, prior art makes often through the thickness for increasing tunnel oxidation layer
The thickness for obtaining the part 1011 that tunnel oxidation layer 101 is located at active-surface region is improved,
For example, in the semiconductor device processing procedure using 55nm process nodes, often by tunnel oxidation
The thickness of layer 101 is from standardBring up toEvenHowever, this method
Tunnel oxidation layer 101 is being improved positioned at the same of the thickness of the part 1011 in active-surface region
When also can improve tunnel oxidation layer 101 positioned at active area central area part thickness, and this
The programmed and erased efficiency of device will be reduced.
As can be seen here, existing semiconductor device exist be difficult in the programming for ensureing p-Flash and
Improve the reading stress and erasing interference performance (read of p-Flash in the case of efficiency of erasing
Stress/erase disturb) technical problem.
Therefore, be solve above-mentioned technical problem, it is necessary to propose a kind of new semiconductor device and
Its manufacture method.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be concrete real
Apply in mode part and further describe.The Summary of the present invention is not meant to
Attempt the key feature and essential features for limiting technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the present invention provides a kind of manufacture method of semiconductor device,
Methods described includes：
Step S101：The hard mask of patterning is formed on a semiconductor substrate, using described hard
Mask performs etching to be formed positioned at active area both sides for housing to the Semiconductor substrate
The groove of shallow trench isolation；
Step S102：Shallow trench isolation is formed in the groove；
Step S103：Remove the hard mask, the quasiconductor corresponding to the active area
Substrate carries out nitrogen injection, to form nitrogen injection region in the Semiconductor substrate, wherein, it is located at
The nitrogen concentration of the nitrogen injection region of the marginal portion of the active area is less than positioned at the active area
The nitrogen concentration of the nitrogen injection region of core；
Step S104：Tunnel oxidation layer is formed in Semiconductor substrate in the active area,
The thickness of the part positioned at active-surface region of wherein described tunnel oxidation layer is more than described
The thickness of the part positioned at active area central area of tunnel oxidation layer；
Step S105：Floating boom is formed on the tunnel oxidation layer.
Further, the nitrogen is injected to inclination injection.
Further, the injection direction for injecting that inclines is with the angular range of vertical direction
10 °～80 °.
Further, step S102 includes：
Deposition shallow trench isolated material is filled the groove and covers the hard mask；
The shallow trench isolated material is planarized, the surface of the hard mask is stopped at
On.
Further, also comprise the steps after step S105：
Step S106：Remove part of the shallow trench isolation higher than the Semiconductor substrate；
Step S107：Form between the grid on the floating boom dielectric layer and positioned at described
Control gate between grid on dielectric layer.
Further, the hard mask includes the first hard mask layer and the disposed thereon second hard mask
Layer.
Further, the material of first hard mask layer be silicon oxide, second hard mask layer
Material be silicon nitride.
Further, the thickness of the part positioned at active area central area of the tunnel oxidation layer is
The embodiment of the present invention two provides a kind of semiconductor device obtained using aforesaid manufacture method
Part.
In sum, the manufacture method of the semiconductor device of the present embodiment, by partly leading described
Nitrogen injection region, and the nitrogen injection region of the marginal portion for making to be located at the active area are formed in body substrate
Nitrogen concentration less than the nitrogen injection region of the core positioned at the active area nitrogen concentration, can be with
So that the thickness that tunnel oxidation layer is located at the part in active-surface region is more than tunnel oxidation layer
Positioned at the part of active area central area, therefore the programmed and erased effect of Flash can ensured
Improve reading stress and the erasing interference performance of Flash in the case of rate, and then improve the good of device
Rate and performance.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is a kind of sectional view of semiconductor device of the prior art；
Fig. 2A to Fig. 2 G is the phase of the manufacture method of the semiconductor device of the embodiment of the present invention one
Close the sectional view (left figure) and top view (right figure) of the structure that step is formed；
Fig. 3 is the schematic stream of the manufacture method of the semiconductor device of embodiments of the invention one
Cheng Tu；
Fig. 4 is a kind of sectional view of semiconductor device of the embodiment of the present invention two.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer and
It is adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and by using from
And an element or feature shown in figure are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operate
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view is describing inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle its edge generally there is circle or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The disposal area formed by injection can cause the surface that the disposal area and injection are passed through when carrying out
Between area in some injection.Therefore, the area for showing in figure is substantially schematic, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below, with reference to Fig. 2A to Fig. 2 G and Fig. 3 come describe the embodiment of the present invention proposition
The manufacture method of semiconductor device.Wherein, Fig. 2A to Fig. 2 G is the embodiment of the present invention one
The sectional view (left figure) of the structure that the correlation step of the manufacture method of semiconductor device is formed and bow
View (right figure)；Fig. 3 is the manufacture method of the semiconductor device of embodiments of the invention one
Indicative flowchart.
The manufacture method of the semiconductor device of the embodiment of the present invention, may include steps of：
First, as shown in Figure 2 A, the hard mask of patterning is formed on semiconductor substrate 200
201, perform etching to form position using 201 pairs of Semiconductor substrates 200 of the hard mask
In the groove 202a for housing shallow trench isolation of active area both sides.
Specifically, wherein the Semiconductor substrate 200 can be in the following material being previously mentioned
It is at least one：Silicon (SSOI), insulation are laminated on silicon, silicon-on-insulator (SOI), insulator
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulation are laminated on body
Germanium (GeOI) etc. on body.Defined active area (AA) in the Semiconductor substrate 200.
Exemplary, hard mask 201 includes the first hard mask layer 201a and disposed thereon the
Two hard mask layer 201b, as shown in Figure 2 A.Wherein, the material of the first hard mask layer 201a
Can be silicon oxide, the material of the second hard mask layer 201b can be silicon nitride.
In one example, forming the method for the groove 202a includes：Defined active
Hard mask 201 is formed in the Semiconductor substrate 200 in area, using photoetching process patterned hard mask
201, the size of the predetermined groove for being formed of the definition of hard mask 201 of patterning, then, to sudden and violent
The Semiconductor substrate of dew is performed etching, to form groove 202a, wherein, the quarter in the step
Etching technique can be using dry etching well known to those skilled in the art or wet etching.
Then, as shown in Figure 2 B, shallow trench isolation 202 is formed in the groove.
Exemplarily, deposit shallow trench isolated material to fill the groove and cover hard mask, it
Afterwards, shallow trench isolated material is planarized, is stopped on the surface of hard mask.Wherein,
The shallow trench isolated material can for silicon oxide, silicon oxynitride, Fluorin doped glass and/or its
Its existing advanced low-k materials.Planarization conventional in field of semiconductor manufacture can be used
Method come realize planarization.The non-limiting examples of the flattening method include machinery planarization side
Method and chemically mechanical polishing flattening method.Chemically mechanical polishing flattening method is more often used.
Then, as shown in Figure 2 C, the hard mask 201 is removed, to active area correspondence
The Semiconductor substrate 200 carry out nitrogen injection, with the Semiconductor substrate 200 formed
Nitrogen injection region, wherein, positioned at the nitrogen of the nitrogen injection region 203a of the marginal portion of the active area
Nitrogen concentration of the concentration less than the nitrogen injection region 203b of the core positioned at the active area.
The method for removing hard mask 201, can be etching or other suitable methods.
Wherein, nitrogen injection can be injected using nitrogen, or other suitable nitrogenous gas or ion
Injection.Exemplarily, the nitrogen is injected to inclination injection, positioned at the edge part of the active area
Nitrogen note of the nitrogen concentration of the nitrogen injection region 203a for dividing less than the core positioned at the active area
Enter the nitrogen concentration of area 203b.Further, the injection direction for inclining injection and vertical side
To angular range be 10 °～80 °.
As shown in Figure 2 D, tunnel oxygen is formed in the Semiconductor substrate 200 in the active area
Change layer 204, wherein the part positioned at active-surface region of the tunnel oxidation layer 204
Part positioned at active area central area of the thickness of 204a more than the tunnel oxidation layer 204
The thickness of 204b.
The tunnel oxidation layer is oxide, and in the present invention optional silicon oxide layer is used as tunnel oxygen
Change layer.In this step as a kind of specific embodiment, can select during silicon oxide layer deposited
Thermal oxide, ald, chemical vapor deposition, electron beam evaporation or magnetically controlled sputter method.
In the present embodiment, because nitrogen injection region can suppress the formation of tunnel oxidation layer, and nitrogen
Concentration it is bigger, it is bigger to the growth inhibition effect of tunnel oxidation layer, therefore, because be located at institute
The nitrogen concentration of nitrogen injection region of the marginal portion of active area is stated less than in the active area
The nitrogen concentration of the nitrogen injection region of center portion point.Therefore the tunnel oxidation layer 204 for ultimately forming
Thickness positioned at the part 204a in active-surface region is more than the tunnel oxidation layer 204
Positioned at the thickness of the part 204b of active area central area.
In the present embodiment, tunnel oxidation layer 204 is located at the part 204b of active area central area
Thickness still using corresponding process node standard thickness, for example, using 55nm technique sections
In the semiconductor device processing procedure of point, tunnel oxidation layer 204 is located at the part of active area central area
The thickness of 204b is still set asLeft and right.
Obviously, using the semiconductor device of said structure, due to tunnel oxidation layer can be caused
The thickness of the 204 part 204b for being located at active area central area keeps constant, thus can protect
The programmed and erased efficiency of card device.Simultaneously as tunnel oxidation layer 204 is located at active area side
The thickness of the part 204a in edge region is improved, therefore is difficult to be compromised, and can avoid depositing
The loss of the electric charge of storage, improves the reading stress and erasing interference performance (read stress/erase of device
disturb)。
As shown in Figure 2 E, floating boom 205 is formed on the tunnel oxidation layer 204.
Wherein, forming the method for floating boom 205 can be：Between adjacent shallow trench isolation 202
Tunnel oxidation layer 204 on deposit floating gate material, and carry out CMP stop at shallow trench every
On 202 surface.
Wherein described floating gate material layer can select semi-conducting material, such as silicon, polysilicon or
Ge etc., it is not limited to a certain material, in this embodiment the floating gate material layer choosing use
Polysilicon.
Alternatively, the deposition process of the floating gate material layer can select molecular beam epitaxy
(MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition
(LPCVD), laser ablation deposition (LAD) and selective epitaxy grow the one kind in (SEG).
In this embodiment, polysilicon is formed from epitaxy method, specifically, is being preferable to carry out
It is described further by taking silicon as an example in example, reacting gas can include hydrogen (H2) carry four
Silicon chloride (SiCl4) or trichlorosilane (SiHCl3), silane (SiH4) and dichloro hydrogen silicon (SiH2Cl2)
It is at least one into the reative cell for being placed with silicon substrate in, carry out high temeperature chemistry in reative cell
Reaction, makes siliceous reacting gas reduce or thermally decompose, and produced silicon atom is in tunnel oxide
Surface Epitaxial growth.
As shown in Figure 2 F, it is higher than the Semiconductor substrate 200 to remove the shallow trench isolation 202
Part.
Wherein, remove what shallow trench isolation 202 was adopted higher than the part of Semiconductor substrate 200
Method can be etching or other suitable methods.Etching both can could also using dry ecthing method
Using wet etch method.Dry ecthing method can be adopted based on the anisotropic etching of carbon fluoride gas
Method.Wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent
(buffer oxide etchant (BOE)) or Fluohydric acid. buffer solution
(buffer solution of hydrofluoric acid(BHF))。
Then, as shown in Figure 2 G, dielectric layer between the grid on the floating boom 205 is formed
206 and the control gate 207 positioned between the grid on dielectric layer 206.
Wherein, dielectric layer 206 can select insulant commonly used in the art, such as oxygen between grid
One or more in compound, nitride.Such as dielectric layer 206 between grid in the present embodiment
Material can be ONO, i.e., including the laminated construction of silicon nitride, silicon oxide and silicon nitride.
The material of control gate 207 can select semi-conducting material, such as silicon, polysilicon or
Ge etc., it is not limited to a certain material, in the present embodiment the material choosing of control gate 207
Use polysilicon.
So far, the committed step of the manufacture method of the semiconductor device of the embodiment of the present invention is completed
Introduction.In embodiments of the present invention, other steps can also be included after control gate is formed,
Here is not defined.
In sum, the manufacture method of the semiconductor device of the present embodiment, by partly leading described
Nitrogen injection region, and the nitrogen injection region of the marginal portion for making to be located at the active area are formed in body substrate
Nitrogen concentration less than the nitrogen injection region of the core positioned at the active area nitrogen concentration, can be with
So that the thickness that tunnel oxidation layer is located at the part in active-surface region is more than tunnel oxidation layer
Positioned at the part of active area central area, therefore the programmed and erased effect of Flash can ensured
Improve reading stress and the erasing interference performance of Flash in the case of rate, and then improve the good of device
Rate and performance.
It is a kind of manufacture method of semiconductor device of one embodiment of the present of invention with reference to Fig. 3
Indicative flowchart, for schematically illustrating the flow process of whole manufacturing process.
Step S101：The hard mask of patterning is formed on a semiconductor substrate, using described hard
Mask performs etching to be formed positioned at active area both sides for housing to the Semiconductor substrate
The groove of shallow trench isolation；
Step S102：Shallow trench isolation is formed in the groove；
Step S103：Remove the hard mask, the quasiconductor corresponding to the active area
Substrate carries out nitrogen injection, to form nitrogen injection region in the Semiconductor substrate, wherein, it is located at
The nitrogen concentration of the nitrogen injection region of the marginal portion of the active area is less than positioned at the active area
The nitrogen concentration of the nitrogen injection region of core；
Step S104：Tunnel oxidation layer is formed in Semiconductor substrate in the active area,
The thickness of the part positioned at active-surface region of wherein described tunnel oxidation layer is more than described
The thickness of the part positioned at active area central area of tunnel oxidation layer；
Step S105：Floating boom is formed on the tunnel oxidation layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also make more kinds of modifications and repair
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Embodiment two
The present invention also provides the semiconductor device that a kind of method in employing previous embodiment one makes
Part, can be flash memory (Flash) device, such as p-Flash, or including flash memories
The semiconductor device of part.The semiconductor device of the embodiment of the present invention is introduced referring to Fig. 4
Typical structure.Wherein, Fig. 4 is a kind of sectional view of the semiconductor device of the embodiment of the present invention.
As shown in figure 4, the semiconductor device of the present embodiment includes Semiconductor substrate 300, is located at
The and of dielectric layer 303 between the tunnel oxidation layer 301, floating boom 302, grid in Semiconductor substrate 300
Control gate 304, wherein, the part 301a positioned at active-surface region of tunnel oxidation layer 301
Thickness more than tunnel oxidation layer 301 the part 301b positioned at active area central area thickness
Degree.
Wherein, tunnel oxidation layer 301 is also referred to as gate dielectric.In the present embodiment, tunnel
Oxide layer 301 is located at the thickness of the part 301b of active area central area and still adopts corresponding technique
The standard thickness of node, for example, in the semiconductor device processing procedure using 55nm process nodes,
Tunnel oxidation layer 301 is located at the thickness of the part 301b of active area central area and is still set asLeft and right.
Obviously, using the semiconductor device of said structure, due to tunnel oxidation layer can be caused
The thickness of the 301 part 301b for being located at active area central area keeps constant, thus can protect
The programmed and erased efficiency of card device.Simultaneously as tunnel oxidation layer 301 is located at active area side
The thickness of the part 301a in edge region is improved, therefore is difficult to be compromised, and can avoid depositing
The loss of the electric charge of storage, improves the reading stress and erasing interference performance (read stress/erase of device
disturb)。
In the present embodiment, the semiconductor device also includes partly being led positioned at the embedded of active area both sides
Shallow trench isolation 3001 in body substrate 300, as shown in Figure 4.
The semiconductor device of the present embodiment is located at active-surface area due to tunnel oxidation layer 301
The thickness of the part 301a in domain is located at the portion of active area central area more than tunnel oxidation layer 301
Divide 301b, therefore Flash can be improved in the case where the programmed and erased efficiency of Flash is ensured
Reading stress and erasing interference performance.
Claims (9)
1. a kind of manufacture method of semiconductor device, including：
Step S101：The hard mask of patterning is formed on a semiconductor substrate, using described hard
Mask performs etching to be formed positioned at active area both sides for housing to the Semiconductor substrate
The groove of shallow trench isolation；
Step S102：Shallow trench isolation is formed in the groove；
Step S103：Remove the hard mask, the quasiconductor corresponding to the active area
Substrate carries out nitrogen injection, to form nitrogen injection region in the Semiconductor substrate, wherein, it is located at
The nitrogen concentration of the nitrogen injection region of the marginal portion of the active area is less than positioned at the active area
The nitrogen concentration of the nitrogen injection region of core；
Step S104：Tunnel oxidation layer is formed in Semiconductor substrate in the active area,
The thickness of the part positioned at active-surface region of wherein described tunnel oxidation layer is more than described
The thickness of the part positioned at active area central area of tunnel oxidation layer；
Step S105：Floating boom is formed on the tunnel oxidation layer.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The nitrogen is injected to inclination injection.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The injection direction for inclining injection is 10 °～80 ° with the angular range of vertical direction.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Step S102 includes：
Deposition shallow trench isolated material is filled the groove and covers the hard mask；
The shallow trench isolated material is planarized, the surface of the hard mask is stopped at
On.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Also comprise the steps after step S105：
Step S106：Remove part of the shallow trench isolation higher than the Semiconductor substrate；
Step S107：Form between the grid on the floating boom dielectric layer and positioned at described
Control gate between grid on dielectric layer.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The hard mask includes the first hard mask layer and the second hard mask layer disposed thereon.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterised in that
The material of first hard mask layer is silicon oxide, and the material of second hard mask layer is nitridation
Silicon.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The thickness of the part positioned at active area central area of the tunnel oxidation layer is
9. a kind of manufacture method using as any one of claim 1 to 8 is obtained
Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510660945.0A CN106601748A (en) | 2015-10-14 | 2015-10-14 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510660945.0A CN106601748A (en) | 2015-10-14 | 2015-10-14 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106601748A true CN106601748A (en) | 2017-04-26 |
Family
ID=58552051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510660945.0A Pending CN106601748A (en) | 2015-10-14 | 2015-10-14 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106601748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192890A (en) * | 2021-04-27 | 2021-07-30 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200841425A (en) * | 2007-04-12 | 2008-10-16 | Promos Technologies Inc | Methods for manufacturing gate structures |
| CN100470738C (en) * | 2003-05-27 | 2009-03-18 | 株式会社东芝 | Method of manufacturing semiconductor device |
| CN102479718A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) |
-
2015
- 2015-10-14 CN CN201510660945.0A patent/CN106601748A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100470738C (en) * | 2003-05-27 | 2009-03-18 | 株式会社东芝 | Method of manufacturing semiconductor device |
| TW200841425A (en) * | 2007-04-12 | 2008-10-16 | Promos Technologies Inc | Methods for manufacturing gate structures |
| CN102479718A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192890A (en) * | 2021-04-27 | 2021-07-30 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100475081B1 (en) | SONOS type EEPROM and method for fabricating the same | |
| CN101432852B (en) | Non-volatile memory device | |
| US7763512B2 (en) | Shallow trench isolation in floating gate devices | |
| CN105493266A (en) | Semiconductor structures and methods of fabrication of same | |
| US8183623B2 (en) | Dual charge storage node memory device and methods for fabricating such device | |
| CN106601744B (en) | A kind of embedded flash memory and its manufacturing method and electronic device | |
| CN104681494A (en) | Semiconductor memory device and preparation method thereof | |
| CN105977259A (en) | Split-gate flash memory layout, mask and manufacturing method | |
| US20070004099A1 (en) | NAND flash memory device and method of manufacturing the same | |
| US10121669B2 (en) | Flash memory fabrication method | |
| CN106611708B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106601748A (en) | Semiconductor device and manufacturing method thereof | |
| CN106972020A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN107437547B (en) | Manufacturing method of semiconductor device | |
| US9224748B2 (en) | Method of forming spaced-apart charge trapping stacks | |
| CN102110658B (en) | Method for fabricating dibit flash memory | |
| KR100814376B1 (en) | Non-volatile memory device and method of manufacturing the same | |
| CN107845637A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN112530974A (en) | Semiconductor structure, integrated circuit and method for forming semiconductor structure | |
| CN107785374A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| US7586145B2 (en) | EEPROM flash memory device with jagged edge floating gate | |
| CN111341778B (en) | NAND flash memory device and forming method | |
| CN108807402A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN108807403A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN1237608C (en) | Method of improving reliability of flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170426 |