CN107785374A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107785374A CN107785374A CN201610719827.7A CN201610719827A CN107785374A CN 107785374 A CN107785374 A CN 107785374A CN 201610719827 A CN201610719827 A CN 201610719827A CN 107785374 A CN107785374 A CN 107785374A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation, and the preparation method includes：Semiconductor substrate is provided, formed with siliceous array of protrusions in the Semiconductor substrate；Current barrier layer is formed on each siliceous raised top.The preparation method can be by forming current barrier layer in siliceous protruding apex, so as to avoid siliceous protruding apex from forming the tip of conduction, and then the relative critical size for increasing siliceous convex top current-carrying part, and leakage current is reduced, improve the device performances such as program window, durability and data holding.The semiconductor devices and electronic installation have higher performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory acts with can repeatedly enter deposit, reading and erasing of row information etc., and be stored in
The characteristic that information will not also disappear after a loss of power, therefore, flash memory has turned into PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storages are due to large storage capacity and relatively high property
Can, it is widely used in the field that read/write requires higher.Recently, the capacity of NAND quick-flash memory chip has reached 2GB, and
Size increases sharply.The solid state hard disc of NAND quick-flash memory chip has been developed based on, and has been used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as the storage device in embedded system, also serves as individual
Storage device in computer system.
As the critical dimension reduction of NAND quick-flash memory memory cell is to below 20nm, floating boom (floating
Gate, FG) critical size it is less and less, and simultaneously because the inter polysilicon such as ONO (oxidenitride oxide)
The thickness of dielectric (IPD) can not reduce always, such as it must keep about 10nm thickness, under the effect of both factors,
As shown in Fig. 1 dashed regions, the critical size at the top of floating boom is very limited (tip in other words, is formed at the top of floating boom), and this leads
Causing during programming, the leakage current in IPD is very big, and then causes maximum threshold voltage in program window greatly to reduce, and
Electron trap (trap) increase in IPD, this will make to device performance, such as program capability, durability, data holding ability etc.
Into influence.
Therefore, it is necessary to a kind of preparation method of new semiconductor devices is proposed, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, the present invention proposes a kind of preparation method of semiconductor devices, it is possible to reduce device is more
The electric leakage of crystal silicon top area, improve the performance and durability of device.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of preparation method of semiconductor devices, the party
Method includes：Semiconductor substrate is provided, formed with siliceous array of protrusions in the Semiconductor substrate；Each described siliceous raised
Top forms current barrier layer.
Further, the step of forming siliceous array of protrusions on the semiconductor substrate includes：Served as a contrast in the semiconductor
Material layer and patterned hard mask layer are formed on bottom；Using the patterned hard mask layer to be siliceous described in mask etching
Material layer is to form siliceous array of protrusions.
Further, the graphical hard mask layer includes oxide.
Further, nitride is also formed between the material layer and the graphical hard mask layer to stop
Layer.
Further, include the step of each siliceous raised top forms current barrier layer：Form filling institute
State the packed layer in siliceous array of protrusions gap；The part packed layer is removed to expose the siliceous raised top；Described
Siliceous raised top forms current barrier layer.
Further, the current barrier layer is nitride.
Further, the siliceous raised top is performed and contains nitrogen plasma treatment, to form the nitride.
Further, described containing nitrogen plasma treatment is N2 or NH3 corona treatments.
Further, the packed layer in the gap is isolation structure oxide.
Further, before the packed layer for filling the siliceous array of protrusions gap is formed, also comprise the steps：With
The patterned hard mask layer is Semiconductor substrate described in mask etching to form the groove for forming isolation structure.
Further, the siliceous array of protrusions is floating polysilicon grid array.
Further, the siliceous array of protrusions is array containing silicon fin.
The preparation method of semiconductor devices proposed by the present invention, by forming current barrier layer in siliceous protruding apex, from
And siliceous protruding apex can be avoided to form the tip of conduction, and then increase the crucial chi of siliceous convex top current-carrying part relatively
It is very little, and leakage current is reduced, improve the device performances such as program window, durability and data holding.
Another aspect of the present invention provides a kind of semiconductor devices made using the above method, and the semiconductor devices includes：
Semiconductor substrate, formed with siliceous array of protrusions in the Semiconductor substrate, and each siliceous raised top formed with
Current barrier layer.
Further, the siliceous array of protrusions is floating polysilicon grid array.
Further, gate dielectric and control grid layer are also formed with the siliceous projection.
Semiconductor devices proposed by the present invention, in siliceous protruding apex formed with current barrier layer, it can so avoid containing
Silicon protruding apex forms the tip of conduction, and then the critical size of the relative siliceous convex top current-carrying part of increase, and reduces Lou
Electric current, improve the device performances such as program window, durability and data holding.
Further aspect of the present invention provides a kind of electronic installation, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with it is similar the advantages of.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the SEM diagrams of the NAND device made in current technique；
Fig. 2 shows the step flow chart of the preparation method of semiconductor device according to the invention；
Fig. 3 A~Fig. 3 G show that the preparation method of semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the diagrammatic cross-section of semiconductor devices；
Fig. 4 shows the step flow chart of the preparation method of semiconductor devices according to an embodiment of the present invention；
Fig. 5 shows the sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 6 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
Identical element is represented with reference.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, NAND quick-flash memory memory cell in current technique, due to critical dimension reduction at the top of floating boom,
And the thickness of inter polysilicon dielectric (IPD) can not reduce always so that floating boom top dimension is less and less, gradually forms point
End, increases electric leakage.Device performance is reduced, the present invention is directed to the above situation, there is provided a kind of preparation method of semiconductor devices,
The semiconductor devices for including siliceous array of protrusions for making NAND etc., it can reduce the siliceous convex of such as floating boom array
The top electric leakage of array is played, improves device performance.As shown in Fig. 2 this method includes：Step 201：Semiconductor substrate, institute are provided
State in Semiconductor substrate formed with siliceous array of protrusions；Step 202：Current blocking is formed on each siliceous raised top
Layer.
The preparation method of semiconductor devices proposed by the present invention, by forming current barrier layer in siliceous protruding apex, from
And siliceous protruding apex can be avoided to form the tip of conduction, and then increase the crucial chi of siliceous convex top current-carrying part relatively
It is very little, and leakage current is reduced, improve the device performances such as program window, durability and data holding.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The preparation method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 3 A~Fig. 3 G and Fig. 4
It is described in detail.
First, as shown in Figure 3A, there is provided Semiconductor substrate 300, formed with floating boom array in the Semiconductor substrate 300
302, formed with the groove for forming isolation structure in the Semiconductor substrate 300, the gap between the floating boom array 302
And isolated material 305 is filled in the groove.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 300
Constituent material select monocrystalline silicon.
Floating boom array 302 is formed in the Semiconductor substrate 300 can be by method commonly used in the art, such as first
Floating gate material layer is formed in Semiconductor substrate 300, floating gate material layer can use the semi-conducting material such as polysilicon, and lead to
Cross selection molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), swash
A kind of formation in light ablation deposition (LAD) and selective epitaxy growth (SEG).Then, figure is formed on floating gate material layer
The hard mask layer 304 of change, exemplarily, in the present embodiment, patterned hard mask layer 304 uses oxide, exemplarily
For PEOX (plasma enhanced oxidation thing), it can be formed by plasma activated chemical vapour deposition.When formation hard mask layer
, can be graphical by conventional lithographic etch process after 304, to define floating boom figure.Then, covered firmly with patterned
Film layer 304 is mask etching floating gate material layer, so as to form floating boom array 302 in Semiconductor substrate 300.
After floating boom array 302 is formed, continue with patterned hard mask layer 304 as mask etching Semiconductor substrate
300, so as to form the groove for forming isolation structure in the semiconductor substrate.Then the ditch is filled with isolated material 305
Gap between groove and the floating boom array 302, isolated material 305 can select the stronger material of suitable filling capacity.Show
Example property, in the present embodiment, isolated material 305 uses oxide, and it can be (high by HARP (high-aspect-ratio technique), HDP
Density plasma) etc. fill process formed, will not be repeated here.
It is understood that processing said structure, can also form any other structure sheaf needed as needed, such as
Grid oxic horizon 301, it is formed between Semiconductor substrate 300 and floating boom 302.Grid oxic horizon 301 illustratively aoxidizes
Silicon layer, it can pass through such as thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer depositions
Product) the methods of formed.
In addition, in the present embodiment, stop-layer 303, stop-layer are also formed between hard mask layer 304 and floating boom 302
303 are illustratively the nitride of such as silicon nitride, and it can pass through PVD (physical vapour deposition (PVD)), CVD (chemical vapor depositions
Product), ALD (ald) the methods of formed, its subsequently carry out isolated material planarization when be used as CMP (chemical machinery throw
Light) stop-layer.
It will also be appreciated that the quantity of the floating boom determines according to device design requirement and specification, in the present embodiment,
6 floating booms are only schematically shown, it does not represent the exact amount of floating boom.
Then, as shown in Figure 3 B, planarization Operation is performed, to remove the part higher than nitride layer 303.
When forming isolated material 305, inevitably at the top of the hard mask layer on formed, therefore pass through such as CMP and (change
Learn machinery planarization), the planarization Operation such as mechanical lapping remove part higher than silicon nitride layer 303, i.e., be with nitride layer 303
Stop-layer performs planarization Operation, to remove the part that packed layer 305 is higher than nitride layer 303.
It is understood that when performing planarization Operation, the oxide skin(coating) 304 as hard mask layer is eliminated in the lump.
Then, as shown in figs. 3 c and 3d, part isolated material 305 is removed, to expose the top of floating boom 302.
Specifically, (etch back) or depression etching (recess) removal part isolated material are etched back to by performing
305, to expose the top of floating boom 302.(the etch back) or depression etching (recess) of being etched back to includes wet etching or dry
Method etching technics.The wet-etching technology includes the wet-etching technologies such as phosphoric acid, hydrofluoric acid, the dry method etch technology
Including but not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.
Exemplarily, in this embodiment, first as shown in Figure 3 C, the He of part isolated material 305 is removed by dry etching
Partial nitridation nitride layer 303.The technological parameter of the dry etching includes：Etching gas includes the gases such as CF4, CHF3, its flow
Respectively 50sccm~500sccm, 10sccm~100sccm, pressure are 2mTorr~50mTorr, wherein, sccm representatives cube
Cm per minute, mTorr represent milli millimetres of mercury.Wherein, the amount of etch-back depends at the top of floating boom needing the amount exposed, or floating
Need to form the thickness of current barrier layer at the top of grid.Exemplarily, in the present embodiment, the top of floating boom 302 is made by etch-back
ExposeThat is the top of floating boom 302 hasPart be not isolated material 305 and surround.
Then, as shown in Figure 3 D, remaining nitride layer 303 is removed by wet etching.Exemplarily, in the present embodiment
In, remaining nitride layer 303 is removed using hot phosphoric acid wet-etching technology.
Then, as shown in FIGURE 3 E, current barrier layer 306 is formed at the top of the floating boom.
Exemplarily, in the present embodiment, current barrier layer 306 uses nitride, such as silicon nitride.It can be by right
Performed at the top of floating boom containing nitrogen plasma treatment to be formed.For example with the top of N2 or NH3 corona treatments floating boom 302, make
The top of floating boom 302 is changed into silicon nitride by polysilicon, so as to form current barrier layer 306.
Then, as illustrated in Figure 3 F, part isolated material 305 is removed, to expose floating boom 302, and shape in the semiconductor substrate
Into isolation structure 307.
Specifically, (etch back) or depression etching (recess) removal part isolated material are etched back to by performing
305, only retain isolated material 305 and be located at part in floating boom bottom and groove, so as to expose the major part of floating boom 302, and
Isolation structure 307 is formed in Semiconductor substrate, for isolating each floating boom 302.It is described to be etched back to (etch back) or depression quarter
Erosion (recess) includes wet etching or dry etch process.The wet-etching technology wet etching such as including hydrofluoric acid
Technique, the dry method etch technology include but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or
Person is cut by laser.Exemplarily, the technological parameter of the dry etching includes：Etching gas includes the gases such as CF4, CHF3, its
Flow is respectively 50sccm~500sccm, 10sccm~100sccm, and pressure is 2mTorr~50mTorr, wherein, sccm is represented
Cc/min, mTorr represent milli millimetres of mercury.
It is understood that in the present embodiment, only removing part isolated material 305, and retain isolated material positioned at floating
The part of grid bottom, it can so limit the gate dielectric layer (dielectric layer between floating boom and control gate) being subsequently formed and not exist
Too deep region is formed.
Finally, as shown in Figure 3 G, gate dielectric 308 is formed on the current barrier layer 306.
Specifically, grid is formed on the current barrier layer 306 by conventional process such as PVD, CVD, ALD first
Dielectric layer 308.Preferably, the gate dielectric 308 uses ONO (oxidenitride oxide) structure, so both has
There is good interface performance, there is higher dielectric constant again.
So far, the processing step that method according to embodiments of the present invention is implemented is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of, such as after the step shown in Fig. 3 G, including the step of formation control gate etc., it is included in the system of the present embodiment
Make in method.
The preparation method for the semiconductor devices that the present embodiment proposes, as shown in figure 4, the preparation method comprises the steps：
Step 401：Semiconductor substrate is provided, on the semiconductor substrate formed with floating boom array, in the semiconductor
Formed with the groove for forming isolation structure in substrate, isolation is filled in the gap and the groove between the floating boom array
Material；
Step 402：Planarization Operation is performed, to remove the part that the isolated material is higher than stop-layer；
Step 403：Part isolated material is removed, to expose at the top of floating boom；
Step 404：Current barrier layer is formed at the top of the floating boom；
Step 405：Part spacer material layer is removed, to expose at the top of floating boom, and forms isolation junction in the semiconductor substrate
Structure；
Step 406：Gate dielectric and control gate are formed on the current barrier layer.
The preparation method for the semiconductor devices that the present embodiment proposes, by forming current barrier layer on floating boom top, so as to
Floating boom top can be avoided to form the tip of conduction, and then the critical size of relative increase floating boom top conductive part, and reduced
Leakage current, improves such as program window, durability and data keep energy device performance.
Although it is understood that in the present embodiment, to be said exemplified by the floating boom array structure for making NAND device
It is bright, but the preparation method not limited to this of the present invention, but can be applied to prevent the electric leakage of siliceous array of protrusions top and it
In his device, such as it can apply in siliceous fin device.
When in applied to siliceous fin device, the gap between fin can fill isolation in above-mentioned making step
Isolated material in structure, its can also but
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, as shown in figure 5, the semiconductor devices bag
Include：Semiconductor substrate 500, formed with isolation structure 501 in Semiconductor substrate 500, the semiconductor lining between isolation structure
Formed with grid oxic horizon 502 on bottom, formed with floating boom 503 on grid oxic horizon 502, formed at the top of floating boom 503
There is current barrier layer 504, in the side wall of floating boom 503 and the top of current barrier layer 504 formed with gate dielectric 505.
Wherein Semiconductor substrate 500 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In the present embodiment, Semiconductor substrate
500 constituent material selects monocrystalline silicon.
Isolation structure 501, the various suitable isolation structures such as STI (shallow trench isolation), isolated material can be used
Oxide, nitride etc. can be selected.Exemplarily, in the present embodiment, isolated material selects oxide.
Grid oxic horizon 502 is illustratively silicon oxide layer, and it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom 503 uses polycrystalline silicon material, and passes through
Conventional lithographic etch process defines figure.
Current barrier layer 504 uses suitable dielectric material, such as oxide, nitride etc..In the present embodiment, example
Property, current barrier layer 504 uses silicon nitride.
Gate dielectric 505 can use suitable material, will not be repeated here.
The semiconductor devices of the present embodiment, on floating boom top formed with current barrier layer, it can so avoid floating boom top
Conductive tip, and then the critical size of relative increase floating boom top conductive part are formed, and reduces leakage current, improvement is such as compiled
Journey window, durability and data are kept can device performance.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, the semiconductor devices includes：Semiconductor substrate, formed with siliceous in the Semiconductor substrate
Array of protrusions, and each siliceous raised top is formed with current barrier layer.
Wherein Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In addition, may be used also in the semiconductor substrate
So that formed with isolation structure, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure is as example.In the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Siliceous array of protrusions is illustratively floating polysilicon grid array or containing silicon fin.
Current barrier layer uses suitable dielectric material, such as oxide, nitride etc..In the present embodiment, it is exemplary
Ground, current barrier layer use silicon nitride.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 6 shows the example of mobile phone.The outside of mobile phone 600 is provided with the display portion being included in shell 601
602nd, operation button 603, external connection port 604, loudspeaker 605, microphone 606 etc..
The electronic installation of the embodiment of the present invention, by the semiconductor devices that is included in siliceous protruding apex formed with electric current
Barrier layer, siliceous protruding apex can be so avoided to form the tip of conduction, and then the relative siliceous convex top conductive part of increase
The critical size divided, and leakage current is reduced, improve such as program window, durability and data keep energy device performance.Therefore should
Electronic installation equally has the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
Semiconductor substrate is provided, formed with siliceous array of protrusions in the Semiconductor substrate；
Current barrier layer is formed on each siliceous raised top.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that shape on the semiconductor substrate
Include into the step of siliceous array of protrusions：
Material layer and patterned hard mask layer are formed on the semiconductor substrate；
Using the patterned hard mask layer as material layer described in mask etching to form siliceous array of protrusions.
3. the preparation method of semiconductor devices according to claim 2, it is characterised in that the graphical hard mask layer bag
Include oxide.
4. the preparation method of semiconductor devices according to claim 3, it is characterised in that in the material layer and institute
State and be also formed with nitride stop-layer between graphical hard mask layer.
5. the preparation method of semiconductor devices according to claim 2, it is characterised in that each described siliceous raised
The step of top formation current barrier layer, includes：
Form the packed layer for filling the siliceous array of protrusions gap；
The part packed layer is removed to expose the siliceous raised top；
Current barrier layer is formed on the siliceous raised top.
6. the preparation method of semiconductor devices according to claim 5, it is characterised in that the current barrier layer is nitridation
Thing.
7. the preparation method of semiconductor devices according to claim 6, the siliceous raised top is performed nitrogenous etc.
Gas ions processing, to form the nitride.
8. the preparation method of semiconductor devices according to claim 7, it is characterised in that described to contain nitrogen plasma treatment
For N2 or NH3 corona treatments.
9. the preparation method of semiconductor devices according to claim 5, it is characterised in that the packed layer in the gap be every
From structure oxide.
10. the preparation method of semiconductor devices according to claim 9, it is characterised in that filling is described siliceous being formed
Before the packed layer in array of protrusions gap, also comprise the steps：
Using the patterned hard mask layer as Semiconductor substrate described in mask etching to form the ditch for forming isolation structure
Groove.
11. the preparation method of semiconductor devices according to claim 1, it is characterised in that the siliceous array of protrusions is
Floating polysilicon grid array.
12. the preparation method of semiconductor devices according to claim 1, it is characterised in that the siliceous array of protrusions is
Array containing silicon fin.
13. the semiconductor devices that a kind of preparation method using as described in claim 1-12 any one makes, its feature exist
In, including：Semiconductor substrate, formed with siliceous array of protrusions in the Semiconductor substrate, and each siliceous raised top
End is formed with current barrier layer.
14. semiconductor devices according to claim 13, it is characterised in that the siliceous array of protrusions is multi-crystal silicon floating bar
Array.
15. semiconductor devices according to claim 14, it is characterised in that be also formed with grid in the siliceous projection
Dielectric layer and control grid layer.
16. a kind of electronic installation, it is characterised in that including the semiconductor device as described in any one in claim 13-16
Part and the electronic building brick being connected with the semiconductor devices.
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| CN118398484A (en) * | 2024-06-14 | 2024-07-26 | 合肥晶合集成电路股份有限公司 | Preparation method of floating gate |
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| US20130105880A1 (en) * | 2011-10-27 | 2013-05-02 | Hong-suk Kim | Nonvolatile memory devices and fabricating methods thereof |
| CN105448703A (en) * | 2014-08-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN105826272A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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| US20130105880A1 (en) * | 2011-10-27 | 2013-05-02 | Hong-suk Kim | Nonvolatile memory devices and fabricating methods thereof |
| CN105448703A (en) * | 2014-08-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
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