CN106201436A - True Random Number Generator based on double coupling Fibonacci oscillation rings - Google Patents
True Random Number Generator based on double coupling Fibonacci oscillation rings Download PDFInfo
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Abstract
The invention discloses a kind of real random number generator based on double coupling Fibonacci oscillation rings, mainly solve the problem that generation true random number speed is low and randomness is poor of real random number generator in prior art.It includes oscillating circuit and sample circuit, this oscillating circuit is made up of several Fibonacci oscillation rings, each Fibonacci oscillation rings includes some XOR gates, same or door and some reversers, XOR gate and with or door quantity equal, XOR gate, with or door and the number of reverser and connected mode thereof determined by the feedback polynomial used when designing.This oscillating circuit is used for producing Random Oscillation signal；This sample circuit is made up of several sampling electronic circuits, samples for the Random Oscillation signal producing oscillating circuit, the output of all sampling electronic circuits through XOR generating rate at the true random number of more than 100Mbit/s.Present configuration is simple, entropy source randomness is good, can be used for secret communication.
Description
Technical field
The invention belongs to digital circuit technique field, particularly relate to a kind of True Random Number Generator, can be used for secret communication.
Background technology
The high real random number generator of safety for cryptographic system it is critical that, they are usually utilized to produce close
Key, initial vector and the random sequence of some antagonism cryptographic attacks.Traditionally, a method being most commonly used to produce true random number
Be by thermal noise amplify, as Peng Haihui, Liu Xinyu, Huang Jie patent (patent publication No.: CN101727308A) integrated circuit in
The production method of true random number, is sampled by the noise producing numeral power supply signal and digital power signal, then uses DES
Data are processed to obtain true random number by algorithm；A kind of profit of the patent (patent publication No.: CN101751240B) of Yu Huihong
With the real random number generator producing random number that compares thermal noises of equal resistors, use comparator that the thermal noise of same resistance is believed
Number compare and to process to obtain random number sequence.The patent of Bai Guoqiang, Zhang Xiaofeng, Chen Hongyi (patent publication No.:
CN101819515A) true random number generation circuit based on circular type shaker and real random number generator, utilize two with defeated
Enter the high-frequency ring oscillating circuit of end and low frequency annular oscillation circuit constitutes true random number generation circuit, then after it is carried out
Process；The patent (patent publication No.: CN102375722A) that Wang Jian, Zhang Hongfei, Cui Ke, plateau, Liang Hao, gold are removed from office is a kind of truly random
Number generation method and generator, utilize the higher-order of oscillation ring of the outside Enable Pin of multiple independent band to produce multipath output signals, from
In choose sampled signal other road signals are carried out sample XOR obtain true random number.
Above-mentioned certain methods is owing to using random external source, so the random number randomness produced is difficult to be protected, when
When assailant controls random external source, these randoms number are used to be and unsafe；Certain methods is based on reverser group
The oscillation rings become produces random number, owing to such oscillation rings is minimum at the randomness of a cycle of oscillation, obtain random
Property higher true random number, it is necessary to wait its randomness cumulative to a certain degree time could sample output, so this type of method can not be produced
The true random number of raw two-forty.
Summary of the invention
Present invention aims to the deficiency of above-mentioned prior art, propose a kind of based on the vibration of double coupling Fibonaccis
The True Random Number Generator of ring, to improve generation speed and the safety of true random number.
For achieving the above object, the present invention includes:
Oscillating circuit, for producing the Random Oscillation signal with random phase offset；
Sample circuit, samples for the Random Oscillation signal producing oscillating circuit, is converted by continuous analog signal
Export for discrete digital signal.
It is characterized in that:
Described oscillating circuit, including:
Several identical double coupling Fibonacci oscillation rings are constituted, wherein:
Each double coupling Fibonacci oscillation rings, including upper and lower two inverter group, k XOR gate XOR and k same or door
The value of XNOR, k determines according to feedback polynomial given during design；
Each reverser group is connected and composed by r inverter series, and the outfan of the most each phase inverter is anti-except last
Outside phase device, it is all connected to the input of next phase inverter, the number of times of feedback polynomial given when r is design；
Each XOR gate XOR and each with or door XNOR all have three input ports and an output port, each XOR
Door XOR is same with each or door XNOR is connected as follows:
The first input port of jth XOR gate XOR and+1 XOR gate XOR of jthj+1Output port connect, second is defeated
Inbound port and jth+1 with or door XNORj+1Output port connect, cj in the 3rd input port and upper reverser group
The output port of reverser connects, wherein, and 1≤j≤k-1；
The value of cj determines according to feedback polynomial given during design.
Jth with or door XNORjFirst input port and jth+1 with or door XNORj+1Output port connect, the
Two input ports and+1 XOR gate XOR of jthj+1Output port connect, the cj of the 3rd input port and lower reverser group
The output port of reverser connects；
Kth XOR gate XORkFirst input port and upper reverser group in the output port company of ck reverser
Connecing, the second input port is connected with the output port of r reverser in upper reverser group, the 3rd input port with self
Output port connects；
Kth with or door XNORkFirst input port and lower reverser group in the output port of ck reverser
Connect, the second input port is connected with the output port of r reverser in lower reverser group, the 3rd input port and self
Output port connect.
The invention have the advantages that as follows:
1. the true random number stability generated is strong, output speed is high.
Due to the fact that by the XOR gate in two independent Fibonacci oscillation rings be attached realizing two striking
Coupling between Fibonacci oscillation rings, it is possible to produce stable chaotic oscillation, utilizes this stable chaotic oscillation to produce stable
True random number at a high speed.
2. due to the fact that the sample circuit using interval sampling pattern, i.e. at two apart from farthest XOR gate and two
Sample on farthest same or door, greatly reduce the dependency of sampled signal, thus improve randomness.
3. the present invention uses feedback polynomial to be designed, owing to different feedback polynomial correspond to the striking ripple of different double coupling
That contract oscillation rings, adds multiformity and the motility of design.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the circuit structure diagram of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with embodiment, to the present invention
It is described in further detail.Should be appreciated that specific embodiment described herein is used only for explaining the present invention, be not used to limit
Determine the present invention.
With reference to Fig. 1, the present invention includes oscillating circuit, sample circuit.Wherein oscillating circuit is coupled striking Poona by several pairs
Contract oscillation rings is constituted, and is used for producing Random Oscillation signal；Sample circuit is made up of several sampling electronic circuits, for vibration electricity
The Random Oscillation signal that road produces is sampled, and the output of electronic circuit of sampling in this sample circuit is electric as this sampling through XOR
The output port on road, exports true random number sequence.
With reference to Fig. 2, oscillating circuit and sample circuit structure to the present invention are described as follows:
Described oscillating circuit, is made up of several pair of coupling Fibonacci oscillation rings, each double coupling Fibonacci vibrations
Ring includes: upper and lower two inverter group, k XOR gate XOR, k with or time door XNOR, k depend on design multinomial to feeding back
Formula；
Feedback polynomial can embody mathematical characteristic that oscillating circuit had and can represent vibration electricity visually
The connected mode of gate in road.The used feedback polynomial of the design is expressed asWherein fiFor feedback
Polynomial coefficient, i is the number of times of independent variable x, f0=fr=1, and when 0 < i < during r, fiValue be 1 or 0, r is feedback polynomial
Number of times, r is the integer not less than 8；
K be 0 < i < in r, all feedback polynomial coefficient fiIntermediate value is the number of 1；
Each reverser group is connected and composed by r inverter series, and the outfan of the most each phase inverter is anti-except last
Outside phase device, it is all connected to the input of next phase inverter；
Each XOR gate XOR and each with or door XNOR all have three input ports and an output port, and each different
Or door XOR is same with each or door XNOR is connected as follows:
Jth XOR gate XORjFirst input port and+1 XOR gate XOR of jthj+1Output port connect, jth
XOR gate XORjThe second input port and jth+1 with or door XNORj+1Output port connect, jth XOR gate XORj's
3rd input port is connected with the output port of cj reverser in upper reverser group, wherein, and 1≤j≤k-1；
Jth with or door XNORjFirst input port and jth+1 with or door XNORj+1Output port connect, jth
Individual with or door XNORjThe second input port and+1 XOR gate XOR of jthj+1Output port connect, jth with or door XNORj
The 3rd input port be connected with the output port of the cj reverser of lower reverser group；
Kth XOR gate XORkFirst input port and upper reverser group in the output port company of ck reverser
Connect, kth XOR gate XORkThe second input port be connected with the output port of r reverser in upper reverser group, kth
Individual XOR gate XORkThe 3rd input port be connected with the output port of self；
Kth with or door XNORkFirst input port and lower reverser group in the output port of ck reverser
Connect, kth with or door XNORkThe second input port be connected with the output port of r reverser in lower reverser group,
Kth with or door XNORkThe 3rd input port be connected with the output port of self.
The feedback polynomial that the value of above-mentioned cj, ck is certainly used when design；
The used feedback polynomial of the design is expressed asWherein fiFor the coefficient of feedback polynomial,
I is the number of times of independent variable x, f0=fr=1, and when 0 < i < during r, fiValue be 1 or 0, r is the number of times of feedback polynomial, and r is the least
In the integer of 8；
By the feedback polynomial coefficient f that all values is 1iSubscript i according to being arranged in a sequence from small to large, can represent
For c1, c2 ..cj ..ck, the value of the jth number during wherein cj is this sequence.
Described sample circuit, by several sampling electronic circuit and i.e. kth+2 XOR gate XOR of XOR gatek+2Constitute.
This each sampling electronic circuit includes: four d type flip flops, is the first d type flip flop D respectively1, the second d type flip flop D2,
3d flip-flop D3, four d flip-flop D4With 1 XOR gate i.e. kth+1 XOR gate XORk+1.These four d type flip flops respectively with vibration
Four XOR gates in double coupling Fibonacci oscillation rings in circuit are connected, the i.e. first trigger D1Input be the first XOR
Door XOR1Output, the second trigger D2Input be the first XOR gate XNOR1Output, the 3rd trigger D3Input be kth
XOR gate XORkOutput, the 4th trigger D4Input be kth with or door XNORkOutput；The output of these four d type flip flops
As kth+1 XOR gate XORk+1Input, kth+1 XOR gate XORk+1Output as the output of sample circuit electronic circuit, institute
There is the output of sampling electronic circuit as kth+2 XOR gate XORk+2Input, kth+2 XOR gate XORk+2Output be whole very with
The output of machine number generator, these four d type flip flops, kth+1 XOR gate XORk+1, kth+2 XOR gate XORk+2During by outside
The clock CLK that clock circuit provides controls, and the peak frequency of clock CLK is 200MHz.
Embodiment:
This example uses feedback polynomial: f (x)=1+x+x3+x5+x13+x16, it is equivalent to feedback polynomialMiddle f0=fr=1, and when 0 < i < during r, its feedback polynomial coefficient f1=f3=f5=f13=1, this feedback
Multinomial coefficient intermediate value is that the number of the coefficient of 1 has 4, i.e. k is 4；
By the feedback polynomial coefficient f that coefficient value is 1iSubscript i according to sequence c1 being arranged in from small to large, c2,
..cj ..ck, be 1,3,5,13；
Feedback polynomial according to being given above: f (x)=1+x+x3+x5+x13+x16, each coupling of design oscillating circuit
Fibonacci oscillation rings includes: upper and lower be respectively arranged with two reverser groups of 16 reversers, four XOR gate that is first XOR gates
XOR1, the second XOR gate XOR2, the 3rd XOR gate XOR3, the 4th XOR gate XOR4Together or door that is first is same or door XNOR with four1、
Second same or door XNOR2, the 3rd with or door XNOR3, the 4th with or door XNOR4, each XOR gate XOR and each same or door XNOR
Connect as follows:
First XOR gate XOR1First input port and the second XOR gate XOR2Output port connect, the first XOR gate
XOR1The second input port and second with or door XNOR2Output port connect, the first XOR gate XOR1The 3rd input port
It is connected with the output port of the 1st reverser in upper reverser group；
First same or door XNOR1First input port with second with or door XNOR2Output port connect, first with or
Door XNOR1The second input port and the second XOR gate XOR2Output port connect, first with or door XNOR1The 3rd input
Port is connected with the output port of the 1st reverser in lower reverser group；
Second XOR gate XOR2First input port and the 3rd XOR gate XOR3Output port connect, the second XOR gate
XOR2The second input port and the 3rd with or door XNOR3Output port connect, the second XOR gate XOR2The 3rd input port
It is connected with the output port of the 3rd reverser in upper reverser group；
Second same or door XNOR2First input port with the 3rd with or door XNOR3Output port connect, second with or
Door XNOR2The second input port and the 3rd XOR gate XOR3Output port connect, second with or door XNOR2The 3rd input
Port is connected with the output port of the 3rd reverser in lower reverser group；
3rd XOR gate XOR3First input port and the 4th XOR gate XOR4Output port connect, the 3rd XOR gate
XOR3The second input port and the 4th with or door XNOR4Output port connect, the 3rd XOR gate XOR3The 3rd input port
It is connected with the output port of the 5th reverser in upper reverser group；
3rd same or door XNOR3First input port with the 4th with or door XNOR4Output port connect, the 3rd with or
Door XNOR3The second input port and the 4th XOR gate XOR4Output port connect, the 3rd with or door XNOR3The 3rd input
Port is connected with the output port of the 5th reverser in lower reverser group；
4th XOR gate XOR4First input port and upper reverser group in the 13rd reverser output port even
Connect, the 4th XOR gate XOR4The second input port be connected with the output port of the 16th reverser in upper reverser group,
Four XOR gate XOR4The 3rd input port be connected with the output port of self；
4th same or door XNOR4First input port and lower reverser group in the 13rd reverser output port even
Connect, the 4th same or door XNOR4The second input port be connected with the output port of the 16th reverser in lower reverser group,
Four same or door XNOR4The 3rd input port be connected with the output port of self.
Sampling electronic circuit four d type flip flops 100MHZ frequency external clock drive under respectively in oscillating circuit
Four XOR gates in double coupling Fibonacci oscillation rings are sampled, the i.e. first trigger D1When 100MHZ frequency outside
To the first XOR gate XOR under clock driving1Sample, the second trigger D2To the under the external clock of 100MHZ frequency drives
One XOR gate XNOR1Sample, the 3rd trigger D3To the 4th XOR gate XOR under the external clock of 100MHZ frequency drives4
Sample, the 4th trigger D4To the 4th same or door XNOR under the external clock of 100MHZ frequency drives4Sample；Should
Four d type flip flop sampled result are through the 5th XOR gate XOR5XOR is as the output of sample circuit electronic circuit, all samplings
The output of circuit is through the 6th XOR gate XOR6XOR output produces the true random sequence of 1000 groups of 1M.
The effect of the present invention can be illustrated by following test:
1, method of testing:
Use the SP800-22 random number examination criteria that American National Standard and technical research institute NIST provide to above-mentioned
The randomness of the true random sequence of 1000 groups of 1M that example produces detects, and this examination criteria comprises 15 detection contents, often
The testing result of one detection generation comprises a P-value value and a percent of pass Propotion value.When P-value value
Be not less than 0.001 and percent of pass value be not less than 0.9806, represent this detection content pass through.
2, testing result:
True random sequence to the 1000 groups of 1M produced with this example, carries with American National Standard and technical research institute NIST
The SP800-22 random number examination criteria of confession detects, result such as table 1
Table 1 test result
| Statistical Test | P-value | Propotion | Result |
| Frequence | 0.659937 | 0.9902 | Pass |
| BlockFrequence | 0.350368 | 0.9922 | Pass |
| CumulativeSums | 0.784843 | 0.9883 | Pass |
| Runs | 0.681807 | 0.9873 | Pass |
| LongestRun | 0.918651 | 0.9873 | Pass |
| Rank | 0.549642 | 0.9922 | Pass |
| FFT | 0.363621 | 0.9902 | Pass |
| OverlappingTemplate | 0.491928 | 0.9902 | Pass |
| Universal | 0.703826 | 0.9883 | Pass |
| LinearComplexity | 0.212153 | 0.9883 | Pass |
| ApproximateEntropy | 0.440591 | 0.9922 | Pass |
| Serial | 0.280016 | 0.9912 | Pass |
| NonOverlappingTemplate | 0.191187 | 0.9873 | Pass |
| RandomExcursions | 0.228806 | 0.9881 | Pass |
| RandomExcursionsVariant | 0.484628 | 0.9898 | Pass |
As seen from Table 1, each index of true random sequence that this example produces all has reached the requirement standard of random number, shows
The random number that this example produces has good randomness.
Examples detailed above only with being embodied as illustrating the implementation method of the present invention, can have various deformation on this basis, this
Within kind structure based on present invention change is all contained in protection scope of the present invention.
Claims (9)
1. real random number generators based on double coupling Fibonacci oscillation rings, including:
Oscillating circuit, for producing the Random Oscillation signal with random phase offset；
Sample circuit, for oscillating circuit produce Random Oscillation signal sample, continuous analog signal is converted into from
Scattered digital signal exports.
It is characterized in that:
Described oscillating circuit, including:
Several identical double coupling Fibonacci oscillation rings are constituted, wherein:
Each double coupling Fibonacci oscillation rings, including upper and lower two inverter group, k XOR gate XOR and k same or door
The value of XNOR, k determines according to feedback polynomial given during design；
Each reverser group is connected and composed by r inverter series, and the outfan of the most each phase inverter removes last phase inverter
Outward, it is all connected to the input of next phase inverter, the number of times of feedback polynomial given when r is design；
Each XOR gate XOR and each with or door XNOR all have three input ports and an output port, each XOR gate XOR
Or door XNOR same with each is connected as follows:
The first input port of jth XOR gate XOR and+1 XOR gate XOR of jthj+1Output port connect, the second input
Mouthful with jth+1 with or door XNORj+1Output port connect, cj in the 3rd input port and upper reverser group is reversely
The output port of device connects, wherein, and 1≤j≤k-1；
The value of cj determines according to feedback polynomial given during design.
Jth with or door XNORjFirst input port and jth+1 with or door XNORj+1Output port connect, second input
Port and+1 XOR gate XOR of jthj+1Output port connect, the cj reverser of the 3rd input port and lower reverser group
Output port connect；
Kth XOR gate XORkFirst input port be connected with the output port of ck reverser in upper reverser group,
Two input ports are connected with the output port of r reverser in upper reverser group, the 3rd input port and the output of self
Port connects；
Kth with or door XNORkFirst input port be connected with the output port of ck reverser in lower reverser group,
Second input port is connected with the output port of r reverser in lower reverser group, and the 3rd input port is defeated with self
Go out port to connect.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Described feedback polynomial, it is expressed asWherein fiFor the coefficient of feedback polynomial, i is independent variable x
Number of times, f0=fr=1；When 0 < i < during r, fi=1 or 0, r are the integer not less than 8.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
The value of k determines according to feedback polynomial given during design, and it is defined below:
Described feedback polynomial, it is expressed asWherein fiFor the coefficient of feedback polynomial, i is from becoming
The number of times of amount x, f0=fr=1, and when 0 < i < during r, fiValue be 1 or 0, r is the integer not less than 8；
The value of k be when 0 < i < during r, all feedback polynomial coefficient fiIntermediate value is the number of 1.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Cj value determines according to feedback polynomial given during design, and it is defined below:
Described feedback polynomial, it is expressed asWherein fiFor the i-th coefficient of feedback polynomial, i is certainly
The number of times of variable x, f0=fr=1, and when 0 < i < during r, fiValue be 1 or 0, r is the integer not less than 8；
By the feedback polynomial coefficient f that all values is 1iSubscript i according to being arranged in a sequence from small to large, it is represented by
C1, c2 ..cj ..ck, cj represents the value of jth number in this sequence.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Described some phase inverters, utilize the basic programmable logic cells of FPGA to realize, and this logical block is by reverse lookup tables LUT
Form with depositor, by look-up tables'implementation reverser pure digi-tal logic, preserve digital state by depositor.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Described some XOR gates, utilize the basic programmable logic cells of FPGA to realize, and this logical block is by XOR look-up table LUT
Form with depositor, by look-up tables'implementation XOR pure digi-tal logic, preserve digital state by depositor.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Described some with or door, utilize the basic programmable logic cells of FPGA to realize, this logical block is by together or look-up table LUT
Forming with depositor, by look-up tables'implementation, same or pure digi-tal logic, preserves digital state by depositor.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that:
Described sample circuit is made up of several sampling electronic circuits, and each sampling electronic circuit is by four d type flip flops D1, D2, D3, D4 and 1
Individual XOR gate i.e. kth+1 XOR gate XORk+1Composition, these four d type flip flops are connected with four XOR gates in oscillating circuit respectively,
The input of the i.e. first trigger D1 is the output of the first XOR gate XOR1, and the input of the second trigger D2 is the first same or door
The output of XNOR1, the input of the 3rd trigger D3 is kth XOR gate XORkOutput, the 4th trigger D4Input be kth
With or door XNORkOutput；These four d type flip flop D1、D2、D3、D4Output as kth+1 XOR gate XORk+1Input, kth+
1 XOR gate XORk+1Output as the output of sample circuit submodule.
Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 8, it is characterised in that:
Four d type flip flop D1、D2、D3、D4With kth+1 XOR gate XORk+1Being controlled by identical clock, this clock is by external clock electricity
Road provides.
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| CN108345446A (en) * | 2018-03-08 | 2018-07-31 | 太原理工大学 | A kind of high speed random-number generating method and device |
| CN111538475A (en) * | 2020-03-25 | 2020-08-14 | 上海交通大学 | FPGA-based true random number generator construction system and method |
| CN107918535B (en) * | 2017-11-17 | 2021-02-19 | 宁波大学 | Metastable state true random number generator realized on FPGA |
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| CN103049242A (en) * | 2012-12-04 | 2013-04-17 | 清华大学 | Digital true random number generator circuit |
| CN103885747A (en) * | 2014-02-27 | 2014-06-25 | 浙江大学 | Low-power-consumption random number generator |
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| CN108345446A (en) * | 2018-03-08 | 2018-07-31 | 太原理工大学 | A kind of high speed random-number generating method and device |
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| CN111538475B (en) * | 2020-03-25 | 2023-06-23 | 上海交通大学 | System and method for constructing true random number generator based on FPGA |
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