WO2019195953A1 - Two-input exclusive-or gate-based low-power consumption random number generation apparatus - Google Patents

Abstract

A two-input exclusive-OR gate-based low-power consumption random number generation apparatus, composed of an entropy source module (100), an entropy sampling module (200) and a clock module (300), wherein the entropy source module (100) is composed of one two-input exclusive-NOR (XNOR) gate, 14 two-input exclusive-OR (XOR) gates and one three-input exclusive-OR (XOR) gate; the entropy sampling module (200) is formed by a D trigger, the trigger being used for sampling and quantifying signals under the control of a clock so as to generate a random number sequence; and the clock module (300) is used for providing the clock for the entropy sampling module (200). According to the apparatus, 0-800 Mbit/s high-quality random numbers are generated, and the apparatus can successfully pass randomness tests of international standards, such as NIST, Diehard and TestU01, and has a higher rate and lower power consumption compared with a three-input exclusive-OR logic gate.

Description

Low-power random number generating device based on two-input XOR gate Technical field

The invention belongs to the field of digital circuit integration, and is a device with simple structure and low power consumption to generate random numbers.

Background technique

Random numbers play an important role in cryptography. Almost all cryptographic algorithms use some data that must be secret to the attacker. For a one-density system, its security depends on the key, including symmetry. The key of the cryptographic algorithm (DES, AES, etc.) and the key pair of the asymmetric cryptographic algorithm (DSA, DSA, etc.), etc., and these keys must be random numbers.

There are two ways to generate random numbers. One is to use software methods, and the other is to use physical random processes in nature (such as thermal noise, cosmic noise, radioactive decay, etc.). For the former, the generation of a random sequence depends on the algorithm used and the initial seed, and has a certain periodicity, and thus is called a pseudo-random number. If an attacker predicts the law of the generation of pseudo-random numbers, the security of the entire system will be threatened.

The true random number is generated based on the physical characteristics of the electronic device itself, has no periodicity, is unpredictable, and is truly safe. Commonly used methods for generating physical random numbers are: amplified noise method, oscillator sampling method and chaotic circuit. Since the amplitude of the thermal noise in the circuit is small, amplification is required; the oscillation sampling is to digitally mix two independent oscillating signals through a D flip-flop, and the high frequency signal is sampled by the low frequency signal, and the random number passing rate generated by this method is low. Post-processing is required; the random number generated by the unpredictable and sensitive dependence of the chaotic circuit on the initial conditions is not ideal. The above three methods bring limitations with the generation and application of random numbers.

Using non-ideal characteristics of XOR logic devices (such as degradation effects, nonlinear time delays, and short pulse suppression) to generate physical random processes (such as phase noise or chaotic signals), and then extract random number sequences from them, becoming a new type of A method of generating a physical random number.

Currently, the use of logic devices to generate physical random numbers mostly adopts three-input XOR and XOR gate logic circuits to form a Boolean network, generate chaotic signals, and quantize the chaotic signal samples to generate random numbers. However, the physical random number generated by this scheme is not effective, and post processing is often required to further improve the quality of the random number. The structure is complicated and the power consumption is large.

Therefore, it is of great significance to invent a random number generating device which is simple in structure, has no post-processing, and has low power consumption and can be tested by random number.

Summary of the invention

The object of the present invention is to solve the problem that the existing random number generating device has the advantages of complicated structure, large power consumption and low generation rate, and an integrated and low power consumption physical random number device is proposed. The entropy source module and the sampling module of the invention are all composed of digital logic devices, and the structure is simple and the manufacturing cost is low. In addition, the entropy source module of the present invention is composed of a two-input XOR gate (XNOR), 14 two-input XOR gates (XOR), and a three-input XOR gate (XOR), compared to a 3-input X-input. The NOR gate (XNOR) and the three-input XOR gate (XOR) form an autonomous Boolean network. The present invention uses a two-input logic gate device to greatly reduce the power consumption level in the case of generating an equivalent quality chaotic signal. The average power consumption of the input single node is about 2.3 times that of the two-input single node (this conclusion is simulated by the Candence software). Thus, the 16-node two-input Boolean network circuit consumes much less power than the three-input Boolean circuit.

The technical solution of the present invention is: a two-input exclusive-OR gate low-power random number generating device, including an entropy source module 100, an entropy sampling module 200, and a clock module 300, wherein

The entropy source module 100 is configured to generate a chaotic signal;

The entropy sampling module 200 is configured to sample and quantize a signal generated by the entropy source module 100 to generate a random sequence.

The clock module 300 is configured to provide a clock signal to the entropy sampling module 200;

The structure of the entropy source module 100 is composed of 15 nodes composed of 15 two-input logic devices and a three-input XOR logic gate 103. The 15 node structure is composed of a two-input XOR logical gate 102. And 14 first input XOR logic gates 101 are connected in a first position, with two input XOR logic gates 102 as the center, and two two-input XOR logic gates 101 respectively distributed on two sides, wherein one side of the two-input XOR logic The gate 101 is arranged from near to far by a node 101-1 to a seven node 101-7, and the other side of the two-input XOR logic gate 101 is arranged from near to far by fourteen nodes 101-14 to eight nodes 101-8 and Seven nodes 101-7 and eight nodes 101-8 are adjacent nodes; two input terminals of each of the 15 nodes are respectively connected to the output ends of the left and right adjacent nodes; node 102 XOR logical gates (XNOR), six Node 101-6, nine node 101-9 XOR logic gate (XOR) outputs are respectively coupled to the input of a three-input XOR logic gate 103; the output of a three-input XOR logic gate 103 (XOR) is coupled to an entropy sample Module 200 performs sampling and quantization.

The entropy source module 100 is composed of 16 nodes, 15 of which are connected end to end, and another node performs XOR processing on three of the nodes; utilizing non-ideal characteristics of the logic gates in the digital logic circuit (eg Degradation effect, nonlinear time delay and short pulse suppression, etc.) and the influence of system noise, the transmission delay between each logic gate is different, and the output of the node exhibits chaotic dynamics as the entropy source.

The sampling module 200 is provided with two signal input terminals and one signal output end, one of the input signals is connected to the output end of the three-input XOR logic gate 103, and the other input signal is connected to the clock module 300, thereby being clocked Under control, the output of the sampling module completes sampling and quantization of the input signal and outputs a stable random bit stream at the output.

The application of the invention adopts the following steps: (1) utilizing the nonlinear characteristics of the digital logic circuit (such as degradation effect, nonlinear time delay and short pulse suppression, etc.) and the influence of system noise, the delay transmission time of each logic gate is different, 16 The nodes interact as a source of random number entropy. The 16 nodes comprise a node composed of a two-input XOR gate and a node composed of 14 two-input XOR gates connected end to end and a node composed of a three-input XOR gate; wherein the first 15 nodes are connected, An output of two adjacent nodes is used as an input of the node, and the XOR logical gate has a function of oscillating; wherein the outputs of the three nodes of nodes 102, 101-6, and 101-9 are used as three-input XOR An input end of the gate, the output end of the three-input XOR gate is connected to the sampling module, and samples and quantizes the generated signal;

(2) The entropy source output of step (1) is sampled by the sampling module using the clock signal to obtain a bit stream with good random characteristics.

The random number generating device is composed of a digital logic gate, has a simple structure and is easy to implement, and has low power consumption, and lays a foundation for realizing random number chip;

Further, the clock signal is provided by an external clock, and the clock signal is ≤1 GHz;

Further, the entropy sampling module is implemented by a D flip-flop, and the D flip-flop has a clock signal output end connected to the external clock signal; and the signal output end of the D flip-flop is connected to the output end of the entropy source signal;

The invention provides a low-power random number generating device based on two-input XOR logic gates, and the advantages and positive effects thereof are as follows:

First, the generated random number sequence has no periodicity, no post-processing is required, and the clock frequency can be adjusted to generate 0-800 Mbit/s. It can pass the international random number industry test standard (NIST, Diehard and TestU01 statistical test) with good random characteristics. Random number.

Second, the system sampling module uses a D flip-flop. During the operation of the flip-flop, the signal at the input end needs to be stable until the rising edge of the clock arrives and the rising edge of the clock arrives. If not, the trigger enters. Metastable state, which in turn increases the randomness of the system;

Third, the system adopts a circuit composed of logic devices, has a simple structure, is easy to implement, and is compatible with different programmable integrated circuits, and has wide applicability;

Fourth, the structure used in the present invention has low power consumption, is easy to implement chip, and has good robustness and robustness with respect to an entropy source composed of a 3-input XOR gate and an XOR gate. External interference is not sensitive.

DRAWINGS

Figure 1 is a block diagram of the present invention.

Figure 2 is a circuit diagram of the apparatus of the present invention.

2: 100: entropy source module; 101: two-input XOR logic gate; 102: two-input XOR logic gate; 103: three-input XOR logic gate; 200: entropy sampling module; 300: clock module.

detailed description

The invention will be further elaborated below in conjunction with specific embodiments.

As shown in FIG. 1 , the present invention includes three modules: an entropy source module 100, an entropy sampling module 200, and a clock module 300;

2 is a circuit structural diagram of a low-power random number generating device based on a two-input XOR gate according to the present invention. The specific generating method steps are as follows:

Step one, using the nonlinear characteristics of the XOR gate in the digital logic circuit (such as degradation effect, nonlinear time delay and short pulse suppression, etc.), the influence of system noise, and the transmission delay between each logic gate as a random number Entropy source 100, random number entropy source 100 is composed of 16 nodes, wherein node 102 is a two-input XOR logical gate, node 101 is a two-input XOR logic gate, and node 103 is also an exclusive OR logic gate; 101 and 102 Both are two-input logic gates connected end to end, and 103 is a three-input XOR logic gate;

As shown in step 1, the two-input XOR logic gate 101 and the two-input XOR logic gate 102 are connected end to end, and the input ends of each node are respectively connected to the outputs of the left and right nodes, that is, the two-input XOR Two inputs of the logic gate 102 are connected to the outputs of the exclusive OR logic gates 101-1, 101-14; two inputs of the exclusive OR logic gate 101-1 and the exclusive OR logic gates 102, 101-2 The outputs are connected; the two inputs of XOR logic gates 101-14 are connected to the outputs of XOR logic gates 102, 101-13; and so on, the two inputs of the XOR logic gates are respectively phased The two outputs of the adjacent OR gate are connected.

The present invention uses the output of the 0 node 102 formed by the node X 101-6, the node 9 101-9 and the exclusive OR non-logic gate formed by the XOR logic gate as the input end of the three-input XOR logic gate 103, the purpose of which is A random sequence with a more uniform random ratio of 0 and 1 is generated.

The entropy source 100 is not driven by an external clock, producing a periodless, unpredictable signal through the nonlinear characteristics of the devices in the logic circuit.

In step two, the entropy source signal, that is, the output of the three-input exclusive OR logic gate 103 is connected to the input end of the entropy sampling module 200, and is sampled by the entropy sampling module 200, thereby outputting a randomly stable bit stream.

The entropy sampling module 200 is implemented by a D flip-flop. The clock signal input end of the D flip-flop is connected to an external clock signal, that is, the clock module 300. At the same time, the input end of the signal is connected to the output end of the upper original signal.

The primary function of clock module 300 is to provide an external clock signal to entropy sampling module 200.

By implementing the above steps, changing the frequency of the external clock, that is, the production rate of the random number, a random number with a frequency range of 0 to 800 MHz that can pass the international random number industry test standard (NIST test, Diehard test, and TestU01 test) can be generated.

Table 1, Table 2, and Table 3 respectively show the test results of NIST, Diehard, and TestU01 tests for generating 800 Mbps random data at 800 MHz clock frequency. We collected 1000 sets of 800 Mbps random number sequences with a capacity of 1 Mbit for NIST testing. The significant level is 0.01, requiring a P-value of greater than 0.01 for each test and a pass rate greater than 0.9856. We collected a 1 Gbit 800 Mbps random number sequence for the Diehard test with a significant level of 0.01, requiring a P-value of greater than 0.01 and less than 0.99 for each test. Passed all test items of TestU01. The final result indicates that the random number test standard is passed, which proves that the random number generated by the method is random.

It can be seen from the above description that the present invention is technically feasible and can be implemented on a programmable logic circuit such as a CPLD or an FPGA, and the circuit structure is simple and easy to set up, and the power consumption is low and the cost is low. This is especially important for applications that encrypt communications, which will further increase the security of the system.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Table I

Statiscal Tests	P-value	Proportion	Result
Frequency	0.686955	991/1000	Success
Block frequency	0.842937	986/1000	Success
Cumulative sums*	0.947308	994/1000	Success
Runs	0.618385	988/1000	Success
Long runs	0.916599	989/1000	Success
Ranks	0.209948	993/1000	Success
FFT	0.899171	986/1000	Success
Nonoverlapping templates*	0.554420	992/1000	Success
Overlapping templates	0.037320	991/1000	Success
Universal	0.864494	985/1000	Success
Approximate entropy	0.286836	989/1000	Success
Random excursion	0.967407	621/621	Success
Random excursion var*	0.191520	619/621	Success
Serial*	0.516113	989/1000	Success
Linear Complexity	0.965860	987/1000	Success

Table II

Statiscal Tests	P-value	Result
Brithday Spacings	0.911382	Success(KS)
Overlapping Permutations	0.373834	Success
Rank of 31×31 matrices	0.349962	Success
Rank of 31×31 matrices	0.334142	Success(KS)
Rank of 6×8 matrices	0.289730	Success
Monkey Test On 20bits	0.14529	Success
Monkey Tests OPSO	0.3033	Success
Monkey Tests OQSO	0.1162	Success
Monkey Tests DNA	0.9868	Success
Count the 1’s in a Stream of bytes	0.320797	Success
Count the 1’s in specified bytes	0.948070	Success
Parking Lot Test	0.459079	Success(KS)
Minimum Distance Test	0.018527	Success(KS)
Random Spheres Test	0.325426	Success(KS)
The Squeeze Test	0.858115	Success
Overlapping Sums Test	0.549077	Success(KS)
Runs Up and Down Test	0.846682	Success(KS)
The Craps Test	0.928898	Success

Table 3

smarsa_Serial Over	Pass	sknuth_Max Oft	Pass
smarsa_Collision Over	Pass	svaria_Sample Prod	Pass
smarsa_Birthday Spacings	Pass	svaria_Sample Corr	Pass
snpair_Close Pairs	Pass	svaria_Appearance Spacings	Pass
sknuth_Simp Poker	Pass	svaria_Weight Distrib	Pass
sknuth_Coupon Collector	Pass	svaria_Sum Collector	Pass

sknuth_Gap	Pass	smarsa_Matrix Rank	Pass
sknuth_Run	Pass	smarsa_Savir2	Pass
sknuth_Permutation	Pass	smarsa_GCD	Pass
sknuth_Collision Permut	Pass	swalk_Random Walk1	Pass
scomp_Linear Comp	Pass	scomp_Lempel Ziv	Pass
sspectral_Fourier3	Pass	sstring_Longest Head Run	Pass
sstring_Periods In Strings	Pass	sstring_Hamming Weight 2	Pass
sstring_Hamming Corr	Pass	sstring_Hamming Indep	Pass
sstring_Run	Pass	sstring_Auto Cor	Pass

Claims (4)

1. A device for generating a low-power random number based on a two-input exclusive-OR gate, comprising: an entropy source module (100), an entropy sampling module (200), and a clock module (300), wherein

   The entropy source module (100) is configured to generate a chaotic signal;

   The entropy sampling module (200) is configured to sample, quantize, and generate a random sequence of signals generated by the entropy source module (100);

   The clock module (300) is configured to provide a clock signal to the entropy sampling module (200);

   The structure of the entropy source module (100) is composed of 15 nodes composed of 15 two-input logic devices and a three-input XOR logic gate (103). The 15 node structure is composed of a two-input XOR. The non-logic gate (102) is formed by connecting the first two bits of the two-input XOR logic gate (101) with the two-input XOR logic gate (102) as the center and seven two-input XOR logic gates on each side ( 101), wherein the two-input XOR logic gate (101) on one side is arranged from near to far according to one node (101-1) to seven nodes (101-7), and the other side of the two-input XOR logic gate (101) ) arranged by near and far according to fourteen nodes (101-14) to eight nodes (101-8) and seven nodes (101-7) and eight nodes (101-8) as adjacent nodes; each of 15 nodes The two input ends of the node are respectively connected to the output ends of the left and right adjacent nodes; the node (102) XOR logical gate, six node (101-6), nine node (101-9) XOR logic gate output are respectively connected to The input of the three-input XOR logic gate (103); the output of the three-input XOR logic gate (103) is connected to the entropy sampling module (200) for sampling and quantization.
2. The apparatus for generating a low-power random number based on two-input exclusive-OR gate according to claim 1, wherein the entropy sampling module (200) is implemented by a D flip-flop, and the clock signal input end of the D flip-flop is connected. External clock signal.
3. The device for generating a low-power random number based on two-input XOR gate according to claim 2, wherein the signal input end of the D flip-flop is connected to the output end of the entropy source node, and the D flip-flop pair is used. The output signal is sampled and quantized, and the sequence outputted at the output has good randomness.
4. The apparatus for generating a low-power random number based on a two-input exclusive-OR gate according to any one of claims 1 to 3, wherein the clock module (300) adopts an external clock, and the clock signal provided by the external clock ≤ 1GHz.

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