[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN106024664A - Metal layer film thickness stack model calibration method and system - Google Patents

Metal layer film thickness stack model calibration method and system Download PDF

Info

Publication number
CN106024664A
CN106024664A CN201610355194.6A CN201610355194A CN106024664A CN 106024664 A CN106024664 A CN 106024664A CN 201610355194 A CN201610355194 A CN 201610355194A CN 106024664 A CN106024664 A CN 106024664A
Authority
CN
China
Prior art keywords
thickness
model
calibration
doe wafer
metal level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610355194.6A
Other languages
Chinese (zh)
Other versions
CN106024664B (en
Inventor
倪念慈
何大权
阚欢
魏芳
朱骏
吕煜坤
张旭升
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201610355194.6A priority Critical patent/CN106024664B/en
Publication of CN106024664A publication Critical patent/CN106024664A/en
Application granted granted Critical
Publication of CN106024664B publication Critical patent/CN106024664B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

The present invention discloses a metal layer film thickness stack model calibration method and system. The method is based on an accurate metal layer chemical mechanical polishing model, metal layer thicknesses of different DOE wafers are predicted by changing input parameters of the model within the prediction ability scope of the model, and a required thickness of a monitor area is output and used in a spectral calibration process. According to the present invention, not only the calibration time is shortened, and the accuracy of the film thickness stack model is increased.

Description

A kind of method and system of metal level thickness stacking model calibration
Technical field
The present invention relates to integrated circuit technology and manufacture field, particularly relate to a kind of metal level thickness stacking model The method and system of calibration.
Background technology
Due to the difference of metal level zones of different pattern density and unlike material, at CMP, (chemical machinery is thrown Light) technique select than difference, metal thickness skewness after causing wafer chemical mechanical lapping to complete, And the uneven electric property having a strong impact on interconnection circuit of metal thickness and the carrying out of subsequent optical carving technology.For The change of effective monitoring metal layer thickness, can be by monitoring monitor after wafer chemical mechanical lapping on line The thickness of pad judges whether this wafer meets technological requirement.
The calibration of present stage metal layer thickness thickness measurement model is under process stabilizing ground premise, according to DOE (Designed Experiment, contrived experiment method) Wafer's (wafers of i.e. different grinding conditions) (Scanning Electronic Microscopy/Transmission Electron Microscope, sweeps SEM/TEM Retouch ultramicroscope/transmission electron microscope) section value calibration, i.e. cut by the SEM/TEM of actual product Sheet obtains the one-tenth-value thickness 1/10 in monitoring region.As it is shown in figure 1, metal layer thickness thickness measurement model in prior art Calibration steps step is as follows: prepare DOE Wafer (DOE wafer);Collect DOE Wafer spectral information Storehouse;Set up thickness stacking model;Carry out DOE Wafer thickness measure;SEM/TEM cuts into slices;Judgement is cut Point positional accuracy also reads slice of data when correct;Judge whether error in measurement is less thanIf measuring Error is less than, then thickness stacking model precision meets the requirements, and calibration completes, otherwise, then need weight Newly set up thickness stacking model.
The metal layer thickness thickness measurement model calibration steps of prior art has the drawback which needs Substantial amounts of Wafer (wafer) cuts into slices, and the cycle is long, consumes a large amount of manpower, material resources and financial resources, more additional section produces Deformation and the deviation of artificial reading so that data reliability is all had a greatly reduced quality.
In sum, calibrate thickness stacking model owing to using slicing mode to go at present, the longest, put into big, Efficiency is low, and the area size that section is checked is limited, the more additional deformation produced and the deviation of artificial reading of cutting into slices All bringing bigger error to model calibration, therefore, the present invention proposes one and uses chemical metal layer accurately Mechanical lapping model obtains the technological means of a series of model calibration data by changing section technological parameter, no Only shorten the time of calibration, and improve the accuracy of thickness stacking model.
Summary of the invention
For the deficiency overcoming above-mentioned prior art to exist, the purpose of the present invention is to provide a kind of metal level thickness The method and system of the calibration of stacking model, it uses the model of chemical metal layer mechanical lapping accurately by changing Become some processes parameter and obtain a series of model calibration data, not only shorten the time of calibration, and improve The accuracy of thickness stacking model.
For reaching above and other purpose, the present invention proposes the method for a kind of metal level thickness stacking model calibration, The method is based on the model of chemical metal layer mechanical lapping accurately, in model prediction limit of power, by changing The DOE chip metal layer thickness that varying model input parameter prediction is different, the thickness in the monitoring region needed for output, And use it for spectroscopic calibration process.
Further, the method comprises the steps:
Step one, prepares DOE wafer;
Step 2, collects DOE wafer spectral information storehouse;
Step 3, according to DOE wafer spectral information, sets up thickness stacking model;
Step 4, carries out DOE wafer thickness measurement, and uses CMP model to be predicted layout data;
Step 5, extracts monitoring region predictive value calibration thickness model, contrast DOE wafer thickness measured value with Difference between predictive value, carries out respective handling according to the result of contrast.
Further, in step one, this DOE wafer is by carrying out chemistry machine after trimming part division technique parameter Tool grinds and obtains, and the process conditions wherein finely tuned include pressure or the milling time that CMP respectively walks.
Further, in step 4, carry out DOE wafer thickness measurement be utilize through heap fold initial The DOE wafer that spectral measurement is different, obtains a series of film thickness value undetermined.
Further, in step 4, CMP model is used to be predicted layout data being to utilize CMP Model Accurate Prediction metal layer image chemistry mechanical lapping complete after the change of metal layer thickness, wherein utilize Initial conditions during CMP model model prediction is consistent with DOE Wafer grinding condition.
Further, in step 5, utilize the one-tenth-value thickness 1/10 in the monitoring region obtained by CMP model prediction Go to calibrate the one-tenth-value thickness 1/10 that initial spectrum measures, the difference between contrast DOE wafer thickness measured value and predictive value Different, if both difference differences are in default scope, then without revising thickness stacking model, otherwise, then need Re-establish thickness stacking model.
Further, in step 3, set up thickness stacking model and i.e. stack spectrum internal model, be by DOE The reflected signal that wafer is corresponding is analyzed setting up and may be used for measuring identical structure specific thickness mobility scale Metal level film thickness value.
Further, identical structure can be Cu Pad structure, Cu Line Array structure or monolayer or The thickness of more metal layers, this specific thickness mobility scale is by the thickness range in DOE wafer monitoring region certainly Fixed.
For reaching above-mentioned purpose, the present invention also provides for a kind of metal level thickness stacking model calibration system, including:
Preparation unit, is used for preparing DOE wafer;
Spectral information collector unit, is used for collecting DOE wafer spectral information storehouse;
Unit set up by model, for according to DOE wafer spectral information, sets up thickness stacking model;
Thickness measure and predicting unit, be used for carrying out DOE wafer thickness measurement, and use CMP model pair Layout data is predicted;
Calibration process unit, extracts monitoring region predictive value calibration thickness model, and contrast DOE wafer thickness is surveyed Difference between value and predictive value, carries out respective handling according to the result of contrast.
Further, this calibration process unit utilizes the thickness in the monitoring region obtained by CMP model prediction Value goes to calibrate the one-tenth-value thickness 1/10 that initial spectrum measures, the difference between contrast DOE wafer thickness measured value and predictive value Different, if both difference differences are in default scope, then without revising thickness stacking model, otherwise, then need Re-establish thickness stacking model.
Compared with prior art, the method and system of a kind of metal level of present invention thickness stacking model calibration are at gold Belong in the layer predictable limit of power of cmp model, by simulation DOE (Design of Experiments) the actual chemical mechanical milling tech of Wafer, can quickly be accurately obtained DOE Wafer prison Control region one-tenth-value thickness 1/10, and be applied to thickness stacking model calibration during, have input little, time-consumingly Few advantage, efficiency significantly improves.
Accompanying drawing explanation
Fig. 1 is the flow chart of steps of the method for the metal level thickness stacking model calibration of prior art;
Fig. 2 is the step stream of the preferred embodiment of the method for the present invention a kind of metal level thickness stacking model calibration Cheng Tu;
Fig. 3 is the system architecture diagram of the present invention a kind of metal level thickness stacking model calibration system.
Detailed description of the invention
Below by way of specific instantiation accompanying drawings embodiments of the present invention, art technology Personnel can be understood further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention Also can be implemented by other different instantiation or be applied, the every details in this specification also can base In different viewpoints and application, under the spirit without departing substantially from the present invention, carry out various modification and change.
Fig. 2 is the step stream of the preferred embodiment of the method for the present invention a kind of metal level thickness stacking model calibration Cheng Tu.As in figure 2 it is shown, the method for the present invention a kind of metal level thickness stacking model calibration, based on accurately Chemical metal layer mechanical lapping model, in model prediction limit of power, by changing mode input parameter (i.e. The grinding condition of simulation DOE Wafer) predict different DOE Wafer metal layer thickness, needed for output The thickness in monitoring region, and uses it for spectroscopic calibration process, specifically includes following steps:
Step 201, prepares DOE Wafer (DOE wafer).This DOE Wafer is by fine setting part Carrying out what cmp obtained after technological parameter, the process conditions wherein finely tuned include: CMP The pressure of (Chemical Mechanical Planarization) respectively step or milling time etc.
Step 202, collects DOE Wafer spectral information storehouse.
Step 203, according to DOE Wafer spectral information, sets up thickness stacking model.I.e. in stacking spectrum Portion's model, it may be used for measuring identical by reflected signal corresponding for DOE Wafer is analyzed foundation The metal level film thickness value of structure specific thickness mobility scale, identical structure here can be Cu Pad structure, Cu Line Array structure or the thickness of single or multiple lift metal level, specific thickness mobility scale is by DOE The thickness range in Wafer monitoring region determines.
Step 204, carries out DOE Wafer thickness measure, and uses CMP model to carry out pre-to layout data Survey.In this step, carrying out DOE Wafer thickness measure is to utilize the initial spectrum folded through heap to measure not Same DOE Wafer, obtains a series of film thickness value undetermined, uses CMP model to carry out pre-to layout data Survey, the change of metal layer thickness after i.e. utilizing CMP model Accurate Prediction metal layer image chemistry mechanical lapping to complete Change, wherein utilize initial conditions during CMP model model prediction consistent with DOE Wafer grinding condition.
Step 205, extracts monitoring region predictive value calibration thickness model.That is, utilization is pre-by CMP model The one-tenth-value thickness 1/10 in the monitoring region recorded goes to calibrate the one-tenth-value thickness 1/10 that initial spectrum measures, if both differences are necessarily In the range of, then without revising thickness stacking model, otherwise, then need to re-establish thickness stacking model.
Step 206, the difference between contrast DOE Wafer thickness measure and predictive value, if both differences are less than Predetermined threshold value, such as, then thickness stacking model precision meets the requirements, otherwise, then need again to build Vertical thickness stacking model.
Fig. 3 is the system architecture diagram of the present invention a kind of metal level thickness stacking model calibration system.Such as Fig. 3 institute Show, one metal level thickness of the present invention stacking model calibration system, including: preparation unit 301, spectral information Collector unit 302, model set up unit 303, thickness measure and predicting unit 304, calibration and processing unit 305。
Wherein, preparation unit 301 is used for preparing DOE Wafer, and this DOE Wafer is by fine setting part Carrying out what cmp obtained after technological parameter, the process conditions wherein finely tuned include: CMP The pressure of (Chemical Mechanical Planarization) respectively step or milling time etc..
Spectral information collector unit 302, is used for collecting DOE Wafer spectral information, sets up spectral information storehouse.
Unit 303 set up by model, for according to DOE Wafer spectral information, sets up thickness stacking model. I.e. stacking spectrum internal model, it is permissible by being analyzed reflected signal corresponding for DOE Wafer setting up For measuring the metal level film thickness value of identical structure specific thickness mobility scale, identical structure here is permissible It is Cu Pad (copper packing) structure, Cu Line Array (copper cash array) structure or single or multiple lift metal The thickness of layer, specific thickness mobility scale is to be determined by the thickness range in DOE Wafer monitoring region.
Thickness measure and predicting unit 304, be used for carrying out DOE Wafer thickness measure, and use CMP mould Layout data is predicted by type.Here carry out DOE Wafer thickness measure to utilize at the beginning of heap is folded The DOE Wafer that beginning spectral measurement is different, obtains a series of film thickness value undetermined, uses CMP model to version Diagram data is predicted, gold after i.e. utilizing CMP model Accurate Prediction metal layer image chemistry mechanical lapping to complete Belong to the change of layer thickness, wherein utilize initial conditions during CMP model model prediction to grind with DOE Wafer Grind consistent.
Calibration and processing unit 305, be used for extracting monitoring region predictive value calibration thickness model, and contrast DOE is brilliant Difference between circle thickness measurements and predictive value, and carry out respective handling according to the result of contrast.That is, school Accurate and processing unit 305 utilizes the one-tenth-value thickness 1/10 monitoring region obtained by CMP model prediction to go calibration initial Spectrometric one-tenth-value thickness 1/10, the difference between contrast DOE wafer thickness measured value and predictive value, if both are poor Different less than predetermined threshold value, such as, then judge that thickness stacking model precision meets the requirements, otherwise, then Need to re-establish thickness stacking model.
In sum, the method and system of a kind of metal level of present invention thickness stacking model calibration are in metal stratification Learn in the predictable limit of power of mechanical lapping model, by simulation DOE (Design of Experiments) The actual chemical mechanical milling tech of Wafer, can quickly be accurately obtained the thickness in DOE Wafer monitoring region Value, and during being applied to thickness stacking model calibration, have and put into little, the fewest advantage, effect Rate significantly improves.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention. Above-described embodiment all can be carried out by any those skilled in the art under the spirit and the scope of the present invention Modify and change.Therefore, the scope of the present invention, should be as listed by claims.

Claims (10)

1. the method for a metal level thickness stacking model calibration, it is characterised in that: the method is based on accurately Chemical metal layer mechanical lapping model, in model prediction limit of power, pre-by changing mode input parameter Survey different DOE chip metal layer thicknesses, the thickness in the monitoring region needed for output, and use it for spectrum Calibration process.
The method of a kind of metal level thickness the most as claimed in claim 1 stacking model calibration, it is characterised in that The method comprises the steps:
Step one, prepares DOE wafer;
Step 2, collects DOE wafer spectral information storehouse;
Step 3, according to DOE wafer spectral information, sets up thickness stacking model;
Step 4, carries out DOE wafer thickness measurement, and uses CMP model to be predicted layout data;
Step 5, extracts monitoring region predictive value calibration thickness model, contrast DOE wafer thickness measured value with Difference between predictive value, carries out respective handling according to the result of contrast.
The method of a kind of metal level thickness the most as claimed in claim 2 stacking model calibration, it is characterised in that: In step one, this DOE wafer carries out what cmp obtained by after trimming part division technique parameter, The process conditions wherein finely tuned include pressure or the milling time that CMP respectively walks.
The method of a kind of metal level thickness the most as claimed in claim 2 stacking model calibration, it is characterised in that: In step 4, carrying out DOE wafer thickness measurement is to utilize the initial spectrum folded through heap to measure different DOE wafer, obtains a series of film thickness value undetermined.
The method of a kind of metal level thickness the most as claimed in claim 4 stacking model calibration, it is characterised in that: In step 4, using CMP model to be predicted layout data is to utilize CMP model Accurate Prediction gold Belong to the change of metal layer thickness after layer pattern cmp completes, wherein utilize CMP model model prediction Time initial conditions consistent with DOE Wafer grinding condition.
The method of a kind of metal level thickness the most as claimed in claim 5 stacking model calibration, it is characterised in that: In step 5, the one-tenth-value thickness 1/10 monitoring region obtained by CMP model prediction is utilized to go to calibrate initial spectrum The one-tenth-value thickness 1/10 measured, the difference between contrast DOE wafer thickness measured value and predictive value, if both differences are poor Different in default scope, then without revising thickness stacking model, otherwise, then need to re-establish thickness stacking Model.
The method of a kind of metal level thickness the most as claimed in claim 2 stacking model calibration, it is characterised in that: In step 3, set up thickness stacking model and i.e. stack spectrum internal model, be by corresponding for DOE wafer anti- Penetrate signal to be analyzed setting up the metal level thickness that may be used for measuring identical structure specific thickness mobility scale Value.
The method of a kind of metal level thickness the most as claimed in claim 7 stacking model calibration, it is characterised in that: Identical structure can be Cu Pad structure, Cu Line Array structure or the thickness of single or multiple lift metal level Degree, this specific thickness mobility scale is determined by the thickness range in DOE wafer monitoring region.
9. a metal level thickness stacking model calibration system, including:
Preparation unit, is used for preparing DOE wafer;
Spectral information collector unit, is used for collecting DOE wafer spectral information storehouse;
Unit set up by model, for according to DOE wafer spectral information, sets up thickness stacking model;
Thickness measure and predicting unit, be used for carrying out DOE wafer thickness measurement, and use CMP model pair Layout data is predicted;
Calibration process unit, extracts monitoring region predictive value calibration thickness model, and contrast DOE wafer thickness is surveyed Difference between value and predictive value, carries out respective handling according to the result of contrast.
10. a kind of metal level thickness stacking model calibration system as claimed in claim 9, it is characterised in that: This calibration process unit utilizes the one-tenth-value thickness 1/10 monitoring region obtained by CMP model prediction to go to calibrate initial light The one-tenth-value thickness 1/10 that spectrum measures, the difference between contrast DOE wafer thickness measured value and predictive value, if both differences Difference is in default scope, then without revising thickness stacking model, otherwise, then need to re-establish thickness heap Folded model.
CN201610355194.6A 2016-05-25 2016-05-25 A kind of metal layer film thickness stacks the method and system of model calibration Active CN106024664B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610355194.6A CN106024664B (en) 2016-05-25 2016-05-25 A kind of metal layer film thickness stacks the method and system of model calibration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610355194.6A CN106024664B (en) 2016-05-25 2016-05-25 A kind of metal layer film thickness stacks the method and system of model calibration

Publications (2)

Publication Number Publication Date
CN106024664A true CN106024664A (en) 2016-10-12
CN106024664B CN106024664B (en) 2019-04-12

Family

ID=57093353

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610355194.6A Active CN106024664B (en) 2016-05-25 2016-05-25 A kind of metal layer film thickness stacks the method and system of model calibration

Country Status (1)

Country Link
CN (1) CN106024664B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109709774A (en) * 2019-03-08 2019-05-03 上海华力微电子有限公司 A method of for improving silicon warp degree and improving alignment precision
CN111276414A (en) * 2020-02-03 2020-06-12 长江存储科技有限责任公司 Detection method and device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299150A (en) * 2007-05-03 2008-11-05 台湾积体电路制造股份有限公司 Method for monitoring and predicting uniformity of a wafer and manufacture method of semiconductor wafer
CN101540270A (en) * 2008-03-20 2009-09-23 华亚科技股份有限公司 System and method for monitoring program
JP2013036881A (en) * 2011-08-09 2013-02-21 Ebara Corp Polishing monitoring method and polishing device
US20140313516A1 (en) * 2013-04-17 2014-10-23 Kla-Tencor Corporation Reducing Registration Error of Front and Back Wafer Surfaces Utilizing a See-Through Calibration Wafer
US20150371134A1 (en) * 2014-06-19 2015-12-24 Semiconductor Manufacturing International (Shanghai) Corporation Predicting circuit reliability and yield using neural networks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299150A (en) * 2007-05-03 2008-11-05 台湾积体电路制造股份有限公司 Method for monitoring and predicting uniformity of a wafer and manufacture method of semiconductor wafer
CN101540270A (en) * 2008-03-20 2009-09-23 华亚科技股份有限公司 System and method for monitoring program
JP2013036881A (en) * 2011-08-09 2013-02-21 Ebara Corp Polishing monitoring method and polishing device
US20140313516A1 (en) * 2013-04-17 2014-10-23 Kla-Tencor Corporation Reducing Registration Error of Front and Back Wafer Surfaces Utilizing a See-Through Calibration Wafer
US20150371134A1 (en) * 2014-06-19 2015-12-24 Semiconductor Manufacturing International (Shanghai) Corporation Predicting circuit reliability and yield using neural networks

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109709774A (en) * 2019-03-08 2019-05-03 上海华力微电子有限公司 A method of for improving silicon warp degree and improving alignment precision
CN111276414A (en) * 2020-02-03 2020-06-12 长江存储科技有限责任公司 Detection method and device

Also Published As

Publication number Publication date
CN106024664B (en) 2019-04-12

Similar Documents

Publication Publication Date Title
US20210090244A1 (en) Method and system for optimizing optical inspection of patterned structures
CN112964689B (en) Method and system for use in measuring one or more features of a patterned structure
US10290088B2 (en) Wafer and lot based hierarchical method combining customized metrics with a global classification methodology to monitor process tool condition at extremely high throughput
US20100249974A1 (en) Advanced process control with novel sampling policy
CN105702595B (en) The yield judgment method of wafer and the changeable quantity measuring method of wafer conformity testing
CN106853610A (en) Polishing pad and its monitoring method and monitoring system
CN108966674A (en) Hybrid measurement system and method for being measured in film
CN103969168A (en) Quantitative determination method for cross section porosity of loose mineral
CN113035735B (en) Method, system, medium, and electronic device for measuring semiconductor structure
CN117140340B (en) Wafer grinding control method, device, equipment and medium
CN113091626B (en) Method for measuring film thickness of semiconductor device
CN103678756A (en) Method and apparatus for creating nondestructive inspection porosity standards
CN106024664A (en) Metal layer film thickness stack model calibration method and system
CN112071765A (en) Method for determining wafer processing parameters and wafer processing method
US11789981B2 (en) Data processing device, data processing method, and non-transitory computer-readable recording medium
CN109314050A (en) The generation of the automatic formulation of chemical mechanical grinding
CN102130032A (en) Online detection method of ion implantation
US9903707B2 (en) Three-dimensional scatterometry for measuring dielectric thickness
CN112729108B (en) Calibration method of optical critical dimension OCD measuring equipment
CN103887198A (en) Method for scanning storage regions without repeated boundaries
CN105428269A (en) Circuit diagram detection method based on packaging substrate
CN104198509B (en) Photomask graphic defect detection system and method
CN103170906B (en) The method of detection grinding technics load effect
CN107908854B (en) Test pattern for modeling chemical mechanical polishing process model
CN104465366B (en) A kind of NDC growth control methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant