CN105977226B - Sealing ring and the method for preventing chip from damaging when cutting - Google Patents
Sealing ring and the method for preventing chip from damaging when cutting Download PDFInfo
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- CN105977226B CN105977226B CN201610596451.5A CN201610596451A CN105977226B CN 105977226 B CN105977226 B CN 105977226B CN 201610596451 A CN201610596451 A CN 201610596451A CN 105977226 B CN105977226 B CN 105977226B
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Abstract
The present invention provides a kind of sealing ring and the methods for preventing chip from damaging when cutting, and the sealing ring includes more metal layers, and multiple metallic channels through the metal layer are provided on wherein at least one layer of metal layer.The metallic channel being located on metal layer in the present invention can not only reduce edge-crowding effect of current, while can also alleviate the difference of the coefficient of expansion of metal layer and inter-metal dielectric layer, reduce stress.In addition, the sealing ring further includes being located at outermost passivation layer, an opening for running through passivation layer is offered on the passivation layer.In one opening of setting on passivation layer in the present invention, so that the crackle that can avoid generating when cutting is transmitted on the passivating film of chip surface, and then can prevent from introducing crackle in the chips.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of sealing ring and prevent chip in cutting when damage
Method.
Background technique
In semiconductor fabrication, wafer is usually cut into chip one by one, then these chips are succeeded
The different semiconductor package of energy.
It is usually provided with sealing ring (Seal Ring) in chip periphery, the sealing ring is by multiple metal layers and to be located at
Inter-metal dielectric layer (ILD) between metal layer is by certain rule composition.The sealing ring can prevent electrostatic in chip
Integrated circuit impacts, and prevents steam or other pollutions, corrosive factor from entering the functions such as integrated circuit, together
When, sealing ring is also used for increasing the interlayer adhesion of chip interior when carrying out wafer cutting, preventing edge break from prolonging inside
It stretches.But sealing ring hinders the intensity of mechanical damage not big enough, is not enough to withstand thermal stress release bring and destroys, crack
It is likely to pass through sealing ring and extends to effective chip area, fundamentally cannot effectively solve bring side in wafer dicing process
Edge rupture.
Especially, with the progress of performance of semiconductor device, the problem of to improve signal transmission delay and crosstalk, it is simultaneously
Parasitic capacitance is reduced, use and SiO are had begun2Compared to lower relative dielectric constant " (low-k is exhausted for low K film
Velum) ".In sealing ring, generally also use " low K film " as inter-metal dielectric layer, but due to the poplar of " low K film " material
Family name's modulus is small, and thermal expansion coefficient is big, and the ability for causing it to resist deformation is poor, therefore is easy in cutting process in cut edge
Crack is generated, the extension in crack will affect the use of chip or even will cause chip and is damaged and scraps.
When therefore, with current cutting technique separating chips, it is easy to cause the chip section being cut open that crackle occurs,
The strength of materials is caused to reduce, and the crackle generated further extends in the effective integrated circuit area of chip, influences chip
Performance even result in scrapping for chip, influence yield.
Summary of the invention
The sealing ring that the purpose of the present invention is to provide a kind of to protect chip injury-free when chip scribing, the sealing
Ring is set to chip periphery, to can effectively prevent the fracture extension generated by cut edge extremely in the cutting process of chip
Chip, and then chip is impacted.To solve existing chip in cutting process, the crackle that chip section generates easily extends
To chip, and then influence the problem of chip performance even results in chip rejection.
In order to solve the above technical problems, the present invention provides a kind of sealing ring, the sealing ring includes the multilayer for stacking setting
Metal layer, wherein multiple metallic channels through the metal layer are provided at least one layer of metal layer.
Optionally, the sealing ring further includes the inter-metal dielectric layer between adjacent metal.
Optionally, in the sealing ring, the inter-metal dielectric layer is insulating film with low dielectric constant.
Optionally, in the sealing ring, the inter-metal dielectric layer is the silica of Fluorin doped.
Optionally, in the sealing ring, the silica of the Fluorin doped is heavy using high-density plasma chemical gas phase
Product technique is formed.
Optionally, in the sealing ring, in the more metal layers, the width positioned at the metal layer of top is greater than
The width of other metal layers, the width refer to that metal layer is parallel to the width in chip surface direction.
Optionally, in the sealing ring, the sealing ring further includes the metal layer positioned at top in more metal layers
On passivation layer.
Optionally, the material of the passivation layer is silicon nitride.
Optionally, in the sealing ring, an opening for running through the passivation layer is offered on the passivation layer
Optionally, in the sealing ring, the opening is annular opening and surrounds the chip.
Optionally, in the sealing ring, the width of the opening is 2~6 μm.
Optionally, in the sealing ring, the metal layer is copper or aluminium.
Optionally, in the sealing ring, the cross sectional shape of the metallic channel is square.
Optionally, in the sealing ring, the side length of the metallic channel is 1~2 μm.
In addition, the side that the present invention also provides a kind of to prevent chip from damaging when cutting using above-described sealing ring
Method, comprising: the sealing ring is arranged in the periphery of Yu Suoshu chip, and the sealing ring includes more metal layers；In at least one layer of gold
Belong to and multiple metallic channels through the metal layer are set on layer.
Optionally, the sealing ring further includes the passivation layer on the metal layer of top in more metal layers.
Optionally, an opening for running through the passivation layer is opened up on Yu Suoshu passivation layer.
Optionally, the width of the opening of the passivation layer is 2~6 μm.
Compared with prior art, sealing ring provided by the invention has the following beneficial effects:
It is multiple through the upper metal layers due to being provided in its upper metal layers in seal ring structure of the invention
Metallic channel, the metallic channel can not only reduce edge-crowding effect of current, also can be relieved the expansion of metal layer and inter-metal dielectric layer
The difference of coefficient avoids metal layer that bulge phenomenon occurs, and so as to reduce stress, in subsequent cutting process, increases sealing ring
Hinder the intensity of mechanical damage.
In addition, there is the passivation layer on the sealing ring one to run through described blunt in sealing ring of the present invention
The opening for changing layer itself is easy to split since the passivation layer is in cutting process, therefore in the presence of having the opening,
The stress that cutting generates is difficult to be transmitted on the passivating film of chip surface, so as to prevent from introducing crackle in the chips.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the sealing ring of the embodiment of the present invention one；
Fig. 2 is the top view of the sealing ring of the not formed passivation layer of the embodiment of the present invention one；
Fig. 3 is the structural schematic diagram of the sealing ring of the embodiment of the present invention two.
Specific embodiment
Semiconductor crystal wafer need to be divided into several chips after complicated manufacturing process.Arrangements of chips is in crystalline substance
The surface on round surface, wafer is provided with Cutting Road along the surrounding of chip, for separating each chip, i.e., between chip and chip
It is provided with Cutting Road.Meanwhile sealing ring is additionally provided in the periphery of chip.The present invention is i.e. by the metal layer of the sealing ring
Upper that multiple metallic channels are arranged and are open in setting one on the passivation layer on the sealing ring, what is generated when preventing wafer from cutting splits
Seam extends to chip area.
To seal ring structure proposed by the present invention and the seal ring structure is used below in conjunction with the drawings and specific embodiments
The anti-method for causing damage to chip in wafer dicing process that terminates in is described in further detail.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Embodiment one
Fig. 1 is the structural schematic diagram of the sealing ring of the embodiment of the present invention one, and Fig. 2 is the not formed blunt of the embodiment of the present invention one
Change the top view of the sealing ring of layer.Referring to figs. 1 and 2, the periphery of chip 300 is provided with sealing ring 100, the chip
Cutting Road 200 is provided between chip.It is usually provided in the Cutting Road 200 and tests structure (not shown), and
It is not provided in the white space of test structure and is filled with insulating film 130.
The sealing ring 100 includes N layers of metal layer 1101,1102 ... 110N and the passivation layer 120 positioned at top,
In be provided with multiple metallic channels 111 through the metal layer at least one layer of metal layer 110.It for convenience of description, will be in more
The metal layer for being located at top in layer metal layer is known as upper metal layers 110N, i.e., the described passivation layer 120 is located at the upper layer metal
On layer 110N.Preferably, the metal layer 110 can be Cu or Al, and the passivation layer 120 can be silicon nitride layer.
In the present embodiment, multiple gold through the upper metal layers 110N are offered on the upper metal layers 110N
Belong to slot 111.In this way, the metallic channel 111 can be such that the edge area on metal layer increases, it is distributed electric current in the metal layer more
Uniformly, so as to reducing edge-crowding effect of current；Secondly, the metallic channel 111 also can be relieved metal layer and inter-metal dielectric layer
Expansion system difference, avoid metal layer occur bulge phenomenon, so as to reduce stress, in subsequent cutting process, increase
The intensity of sealing ring obstruction mechanical damage.
Refering to what is shown in Fig. 2, the cross sectional shape (plan view shape) of the metallic channel 111 can be rectangle, square or circle
Shape etc..Wherein, when the plan view shape of metallic channel 111 is square, the side length of the metallic channel 111 can be 1~2 μm.Institute
It states metallic channel 111 to be uniformly distributed, and surrounds the chip 300, can get preferable effect in this way.
Shown in continuing to refer to figure 1, the sealing ring 100 further includes electricity Jie between metal positioned at the metal layer 110 between
Matter layer 130.Preferably, the inter-metal dielectric layer 130 is insulating film with low dielectric constant.For example, the inter-metal dielectric layer
It can be using the silica of F doping.Due to the silica of the F doping as insulating film with low dielectric constant, preparation process, structure
With performance closer to silica, and its dielectric constant can satisfy the 0.18um even requirement of 0.13um integrated circuit.
Further, the formation of the silica of the F doping can use high density plasma CVD
The method of (High Density Plasma, HDP).High-density plasma gas-phase deposition is due to can be same in the reactor chamber
Step deposition and etching dielectric, realize the excellent filling at a lower temperature to high depth than gap, what is deposited is exhausted
Edge deielectric-coating has many advantages, such as high density, low impurity defect, while having excellent adhesive capacity to silicon wafer.
Preferably, the upper metal layers 110N is extended into a size value added along its width direction, i.e., in multiple layer metal
In layer, metal layer, that is, upper metal layers 110N width W2 of top is greater than the width W1 of other metal layers, and the width is
Refer to that metal layer is parallel to the width in chip surface direction.In the present embodiment, by by the upper metal layers 110N toward Cutting Road
200 Directional Extension, one size value added, so that the area for the insulating film being located in Cutting Road 200 be made to reduce.It is cut in general, being filled in
Cutting insulating film in 200 is silica, such as resists the silica that the F of the ability difference of deformation is adulterated, crisp due to silica
Property, therefore the stress generated when cutting easilys lead to it and ruptures, and there is the metal of preferable ductility by increasing
The area of layer, reduces the area of silica with this, so as to be reduced to the probability for generating rupture when wafer cutting.In addition, by
It is usually provided with test structure in Cutting Road, therefore when carrying out the extension of upper metal layers, need to ensure not influence test knot
The size of the detection welding pad of structure can make the Cutting Road between chip and chip too narrow, to make to survey if extension is oversized
The size of test weld pad is unsatisfactory for requiring, and then makes the detection for testing device will be more difficult.
Embodiment two
Fig. 3 is the cross-sectional view of the seal ring structure of the embodiment of the present invention two, as shown in figure 3, compared with embodiment one, this reality
It applies in example, the opening 121 for running through passivation layer 120 with one on the passivation layer 120.
Usually after the completion of the manufacturing process of chip, to protect the circuit in chip, therefore it can be covered in the surface of chip
One passivation layer is again covered with the protective layer as protective layer in Cutting Road 200, wherein the protective layer and sealing ring
In passivation layer 120 be formed in same technical process.Since the passivation layer 120 is in cutting process, itself it is easy to split,
Therefore in the presence of having the opening 121, the stress for cutting generation is difficult to be transmitted on the passivation layer of chip surface, from
And it can prevent from introducing crackle in the chips.
The opening 121 of the passivation layer 120 can mutually stagger in the horizontal direction with the metallic channel 111, that is, be open
121 in the surface of metallic channel 111.Certainly, the present invention does not limit 121 position of opening, metallic channel 111 just
Top can also realize the purpose of the present invention.
In the present embodiment, the opening 121 is annular opening, surrounds the chip 300.Preferably, run through the passivation
The width of the opening 121 of layer 120 is 2~6 μm.
In addition, the side that the present invention also provides a kind of to prevent chip from damaging when cutting using sealing ring as described above
Method, comprising: sealing ring as described above is set in the periphery of chip, i.e., the described sealing ring has more metal layers；And in extremely
Multiple metallic channels through the metal layer are provided on few one layer of metal layer.
In addition, the sealing ring further includes the passivation layer of the top of the metal layer positioned at top, the passivation layer and position
It is formed in same technical process in the protective layer of the chip surface, i.e., the described protective layer and the passivation layer can be nitridation
Silicon layer.Preferably, an opening for running through the passivation layer is opened up on the passivation layer in Yu Suoshu sealing ring.
As described above, in the present invention, by the way that multiple metallic channels are arranged on the metal layer in sealing ring and in passivation layer
Upper one opening of setting extends in the crack that cut edge generates to chip, to prevent in wafer dicing process to influence core
The use of piece even results in chip and is damaged and scraps.Wherein, the metallic channel can be relieved metal layer and inter-metal dielectric layer
The difference of the coefficient of expansion reduces stress；In one opening of setting on passivation layer, to can avoid the stress transfer generated when cutting in place
In on the passivating film of chip surface, to prevent from introducing crackle in the chips.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (18)
1. a kind of sealing ring, the sealing ring includes the more metal layers for stacking setting, it is characterised in that: at least one layer of metal layer
On be provided with multiple metallic channels through the metal layer, the sealing ring is cyclic structure, and multiple metallic channels are along institute
The cyclic structure arrangement of sealing ring is stated, and the opening size of the metallic channel is less than the width dimensions of the metal layer,
So that each side wall of the metallic channel is electrically connected with each other.
2. sealing ring as described in claim 1, it is characterised in that: the sealing ring further includes between adjacent metal
Inter-metal dielectric layer.
3. sealing ring as claimed in claim 2, it is characterised in that: the inter-metal dielectric layer is low dielectric constant insulation
Film, the dielectric constant of the insulating film with low dielectric constant are lower than the dielectric constant of silica.
4. sealing ring as claimed in claim 3, it is characterised in that: the inter-metal dielectric layer is the silica of Fluorin doped.
5. sealing ring as claimed in claim 4, it is characterised in that: the silica of the Fluorin doped uses high-density plasma
Chemical vapor deposition process is formed.
6. sealing ring as described in claim 1, it is characterised in that: in the more metal layers, positioned at the metal of top
The width of layer is greater than the width of other metal layers, and the width refers to that metal layer is parallel to the width in chip surface direction.
7. sealing ring as described in claim 1, it is characterised in that: the sealing ring further includes being located in more metal layers most to push up
Passivation layer on the metal layer in portion.
8. sealing ring as claimed in claim 7, it is characterised in that: the material of the passivation layer is silicon nitride.
9. sealing ring as claimed in claim 7, it is characterised in that: offer one on the passivation layer through the passivation layer
Opening.
10. sealing ring as claimed in claim 9, it is characterised in that: the opening is annular opening and surrounds chip.
11. sealing ring as claimed in claim 9, it is characterised in that: the width of the opening is 2~6 μm.
12. sealing ring as described in claim 1, it is characterised in that: the metal layer is copper or aluminium.
13. sealing ring as described in claim 1, it is characterised in that: the cross sectional shape of the metallic channel is square.
14. sealing ring as claimed in claim 13, it is characterised in that: the side length of the metallic channel is 1 μm~2 μm.
15. a kind of sealing ring using as described in one of claim 1-14 prevents chip side for damaging when cutting
Method, it is characterised in that:
The sealing ring is set in the periphery of the chip, the sealing ring includes more metal layers；
In multiple metallic channels through the metal layer are arranged at least one layer of metal layer, multiple metallic channels are around the core
Piece, and the opening size of the metallic channel is less than the width dimensions of the metal layer, so that each side wall of the metallic channel
It is electrically connected with each other.
16. the method for preventing chip from damaging when cutting as claimed in claim 15, it is characterised in that: the sealing ring also wraps
Include the passivation layer being located in more metal layers on the metal layer of top.
17. the method for preventing chip from damaging when cutting as claimed in claim 16, it is characterised in that: on Yu Suoshu passivation layer
Open up an opening for running through the passivation layer.
18. the method for preventing chip from damaging when cutting as claimed in claim 17, it is characterised in that: the passivation layer is opened
The width of mouth is 2 μm~6 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596451.5A CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596451.5A CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
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| Publication Number | Publication Date |
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| CN105977226A CN105977226A (en) | 2016-09-28 |
| CN105977226B true CN105977226B (en) | 2019-07-23 |
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| CN201610596451.5A Active CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878378A (en) * | 2017-05-11 | 2018-11-23 | 台湾积体电路制造股份有限公司 | Three-dimensional integrated circuit structure and its manufacturing method |
| CN109920756A (en) * | 2019-03-20 | 2019-06-21 | 德淮半导体有限公司 | Chip sealing ring and forming method thereof |
| CN115265608A (en) * | 2021-04-30 | 2022-11-01 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1753169A (en) * | 2004-09-24 | 2006-03-29 | 松下电器产业株式会社 | Electronic device and method for fabricating the same |
| CN1770432A (en) * | 2004-09-13 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Seal ring structure for integrated circuit chips |
| CN1988155A (en) * | 2005-12-22 | 2007-06-27 | 中芯国际集成电路制造(上海)有限公司 | Seal ring structure with incomplete contact through hole stack |
| CN101615598A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | The protection sealing ring of the stress that is used to prevent that die separation from causing |
| CN101950743A (en) * | 2009-07-08 | 2011-01-19 | Lsi公司 | To the inhibition of breaking in the integrated circuit of cutting |
-
2016
- 2016-07-27 CN CN201610596451.5A patent/CN105977226B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1770432A (en) * | 2004-09-13 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Seal ring structure for integrated circuit chips |
| CN1753169A (en) * | 2004-09-24 | 2006-03-29 | 松下电器产业株式会社 | Electronic device and method for fabricating the same |
| CN1988155A (en) * | 2005-12-22 | 2007-06-27 | 中芯国际集成电路制造(上海)有限公司 | Seal ring structure with incomplete contact through hole stack |
| CN101615598A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | The protection sealing ring of the stress that is used to prevent that die separation from causing |
| CN101950743A (en) * | 2009-07-08 | 2011-01-19 | Lsi公司 | To the inhibition of breaking in the integrated circuit of cutting |
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| CN105977226A (en) | 2016-09-28 |
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