CN105977226A - Seal ring and method for preventing chip from being damaged during cutting - Google Patents
Seal ring and method for preventing chip from being damaged during cutting Download PDFInfo
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- CN105977226A CN105977226A CN201610596451.5A CN201610596451A CN105977226A CN 105977226 A CN105977226 A CN 105977226A CN 201610596451 A CN201610596451 A CN 201610596451A CN 105977226 A CN105977226 A CN 105977226A
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- sealing ring
- metal
- chip
- passivation layer
- metal level
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- 238000005520 cutting process Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 89
- 239000002184 metal Substances 0.000 claims abstract description 89
- 238000002161 passivation Methods 0.000 claims abstract description 46
- 238000007789 sealing Methods 0.000 claims description 73
- 230000006378 damage Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 71
- 230000035882 stress Effects 0.000 description 8
- 208000037656 Respiratory Sounds Diseases 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Dicing (AREA)
Abstract
The invention provides a seal ring and a method for preventing a chip from being damaged during cutting. The seal ring comprises a plurality of metal layers, wherein at least one metal layer is provided with a plurality of metal grooves running through the metal layer. The metal grooves in the metal layer not only can reduce current edge-crowding effect, but also can reduce expansion coefficient difference between the metal layer and an intermetal dielectric layer, and thus stress is reduced. Besides, the seal ring also comprises a passivation layer arranged on the outermost layer. The passivation layer is provided with an opening running through the passivation layer. The passivation layer is provided with the opening, thereby preventing cracks generated during cutting from being transmitted to the passivation film on the surface of the chip, and preventing the chip from being cracked.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly to a kind of sealing ring and prevent chip in
The method of damage during cutting.
Background technology
In semiconductor fabrication, it is common that wafer is cut into chip one by one, then by these
Chip makes the semiconductor package that function is different.
Being usually provided with sealing ring (Seal Ring) in chip periphery, described sealing ring is by multiple metals
Layer and the inter-metal dielectric layer (ILD) between metal level are by certain rule composition.This sealing
Ring can prevent electrostatic from impacting the integrated circuit in chip, and prevent steam or other contaminatives,
Corrosive factor enters the functions such as integrated circuit, and meanwhile, sealing ring is also used for carrying out wafer cutting
Time, increase the interlayer adhesion of chip internal, prevent edge break from extending inside.But, sealing ring
The insufficient strength hindering mechanical damage is big, is not enough to withstand thermal stress and discharges the destruction brought, crack
It is likely to pass through sealing ring and extends to effective chip area, it is impossible to the most effectively solve wafer cutting
During the edge break that brings.
Especially, along with the progress of performance of semiconductor device, for improving signal transmission delay and crosstalk
Problem, simultaneously for reducing parasitic capacitance, has begun to use and SiO2Compare and there is relatively low relative dielectric
" low K film (insulating film with low dielectric constant) " of constant.In sealing ring, generally also use " low K
Film " as inter-metal dielectric layer, but owing to the Young's modulus of " low K film " material is little, heat is swollen
Swollen coefficient is big, causes the ability of its opposing deformation, is therefore easy in cutting process at cutting edge
Edge produces crack, and the extension in crack can affect the use of chip and chip even can be caused impaired and scrap.
Therefore, when using current cutting technique separating chips, it is easy to cause the chip being cut open to break
There is crackle in face, causes the strength of materials to reduce, and the crackle produced further extends to having of chip
In the integrated circuit district of effect, the performance affecting chip even results in scrapping of chip, affects yield.
Summary of the invention
It is an object of the invention to provide a kind of sealing protecting chip injury-free when chip scribing
Ring, described sealing ring is arranged at chip periphery, thus in the cutting process of chip, can effectively prevent
The fracture extension produced by cut edge is to chip, and then impacts chip.Existing to solve
Chip is in cutting process, and the crackle that chip section produces easily extends in chip, and then affects chip
The problem that performance even results in chip rejection.
For solving above-mentioned technical problem, the present invention provides a kind of sealing ring, and described sealing ring includes stacking
The more metal layers arranged, wherein, at least one of which metal level is provided with and multiple runs through described metal level
Metallic channel.
Optionally, described sealing ring also includes the inter-metal dielectric layer between adjacent metal.
Optionally, in described sealing ring, described inter-metal dielectric layer is insulating film with low dielectric constant.
Optionally, in described sealing ring, described inter-metal dielectric layer is the silicon oxide of Fluorin doped.
Optionally, in described sealing ring, the silicon oxide of described Fluorin doped uses high-density plasma
Chemical vapor deposition method is formed.
Optionally, in described sealing ring, in described more metal layers, it is positioned at the metal of top
The width of layer is more than the width of other metal level, and described width refers to that metal level is parallel to chip surface side
To width.
Optionally, in described sealing ring, described sealing ring also includes being positioned in more metal layers and pushes up most
Passivation layer on the metal level in portion.
Optionally, the material of described passivation layer is silicon nitride.
Optionally, in described sealing ring, described passivation layer offers one and runs through described passivation layer
Opening
Optionally, in described sealing ring, described opening is annular opening and surrounds described chip.
Optionally, in described sealing ring, the width of described opening is 2～6 μm.
Optionally, in described sealing ring, described metal level is copper or aluminum.
Optionally, in described sealing ring, the cross sectional shape of described metallic channel is square.
Optionally, in described sealing ring, the length of side of described metallic channel is 1～2 μm.
Additionally, the present invention also provides for the above-described sealing ring of a kind of employing to prevent chip in time cutting
The method of damage, including: arrange described sealing ring in the periphery of described chip, described sealing ring includes
More metal layers；Multiple metallic channel running through described metal level is set at least one of which metal level.
Optionally, described sealing ring also includes being positioned in more metal layers on the metal level of top
Passivation layer.
Optionally, on described passivation layer, an opening running through described passivation layer is offered.
Optionally, the width of the opening of described passivation layer is 2～6 μm.
Compared with prior art, the sealing ring that the present invention provides has the advantages that
In the seal ring structure of the present invention, owing to being provided with multiple running through on described in its upper metal layers
The metallic channel of layer metal level, described metallic channel not only can reduce edge-crowding effect of current, also can alleviate metal
The difference of the coefficient of expansion of layer and inter-metal dielectric layer, it is to avoid metal level generation bulge phenomenon, thus can
Reduce stress, in follow-up cutting process, increase sealing ring and hinder the intensity of mechanical damage.
Additionally, in sealing ring of the present invention, the passivation layer being positioned on described sealing ring has one
Run through the opening of described passivation layer, owing to described passivation layer is in cutting process, itself easily split,
Therefore, in the presence of having described opening, the stress that cutting produces is difficult to be delivered to the passivation of chip surface
On film such that it is able to prevent from introducing in the chips crackle.
Accompanying drawing explanation
Fig. 1 is the structural representation of the sealing ring of the embodiment of the present invention one；
Fig. 2 is the top view of the sealing ring not forming passivation layer of the embodiment of the present invention one；
Fig. 3 is the structural representation of the sealing ring of the embodiment of the present invention two.
Detailed description of the invention
Semiconductor crystal wafer, after complicated manufacturing process, need to be divided into several chips.Core
Sheet is arranged in the surface of wafer, and the surface of wafer is provided with Cutting Road along the surrounding of chip, is used for separating
Each chip, is i.e. provided with Cutting Road between chip and chip.Meanwhile, the periphery at chip also sets up
There is sealing ring.The present invention is i.e. by arranging multiple metallic channel and in institute on the metal level of described sealing ring
Stating and arrange an opening on the passivation layer on sealing ring, the fracture extension produced during to prevent wafer from cutting is extremely
Chip area.
The seal ring structure that the present invention proposed below in conjunction with the drawings and specific embodiments and use described close
Seal ring structure is prevented terminating in chip is caused in wafer dicing process the method for damage make the most specifically
Bright.According to following explanation and claims, advantages and features of the invention will be apparent from.Need explanation
, accompanying drawing all uses the form simplified very much and all uses non-ratio accurately, only in order to convenient,
Aid in illustrating the purpose of the embodiment of the present invention lucidly.
Embodiment one
Fig. 1 is the structural representation of the sealing ring of the embodiment of the present invention one, and Fig. 2 is the embodiment of the present invention
The top view of the sealing ring not forming passivation layer of.Shown in Fig. 1 and Fig. 2, in chip 300
Periphery be provided with sealing ring 100, be provided with Cutting Road 200 between described chip and chip.Described cut
It is usually provided with test structure (not shown) in cutting 200, and is not provided with testing the sky of structure
Dielectric film 130 all it is filled with in white region.
Described sealing ring 100 includes N shell metal level 1101,1102 ... 110N and be positioned at top
Passivation layer 120, at least a part of which has on layer of metal layer 110 to be provided with and multiple runs through described metal level
Metallic channel 111.For convenience of description, the metal level being positioned at top in more metal layers is referred to as upper strata
Metal level 110N, the most described passivation layer 120 is positioned in described upper metal layers 110N.Preferably,
Described metal level 110 can be Cu or Al, and described passivation layer 120 can be silicon nitride layer.
In the present embodiment, described upper metal layers 110N offers and multiple runs through described upper strata metal
The metallic channel 111 of layer 110N.So, described metallic channel 111 can make the edge area on metal level increase
Many, make electric current more uniformly spread in the metal layer, thus edge-crowding effect of current can be reduced；Secondly,
Described metallic channel 111 also can alleviate the difference of the expansion system of metal level and inter-metal dielectric layer, it is to avoid
Metal level generation bulge phenomenon, thus stress can be reduced, in follow-up cutting process, increase and seal
Ring hinders the intensity of mechanical damage.
With reference to shown in Fig. 2, the cross sectional shape (plan view shape) of described metallic channel 111 can be rectangular
Shape, square or circular etc..Wherein, when the plan view shape of metallic channel 111 is square, described
The length of side of metallic channel 111 can be 1～2 μm.Described metallic channel 111 is uniformly distributed, and surrounds described
Chip 300, so can obtain preferably effect.
With continued reference to shown in Fig. 1, described sealing ring 100 also includes between described metal level 110
Inter-metal dielectric layer 130.Preferably, described inter-metal dielectric layer 130 is low-k
Dielectric film.Such as, this inter-metal dielectric layer can use the silicon oxide that F adulterates.Due to as low
The silicon oxide of the F doping of dielectric coefficient insulation film, its preparation technology, structure and performance are closer to dioxy
SiClx, and its dielectric constant can meet the requirement of 0.18um even 0.13um integrated circuit.
Further, the formation of the silicon oxide of described F doping can use high-density plasma chemical
The method of vapour deposition (High Density Plasma, HDP).High-density plasma vapour deposition work
Skill is owing to can synchronize deposition and etching dielectric in the reactor chamber, it is achieved that the most right
The excellent filling of high depth than gap, its dielectric insulating film deposited has high density, and low impurity lacks
Fall into etc. advantage, silicon chip is had excellent adhesive capacity simultaneously.
Preferably, described upper metal layers 110N is extended a size value added along its width, i.e.
In more metal layers, the width W2 of i.e. upper metal layers 110N of the metal level of top is more than other
The width W1 of metal level, described width refers to that metal level is parallel to the width in chip surface direction.This reality
Execute in example, by by described upper metal layers 110N toward Cutting Road 200 Directional Extension one size value added,
So that the area being positioned at the dielectric film of Cutting Road 200 reduces.Generally, Cutting Road 200 it is filled in
Interior dielectric film is silicon oxide, such as, resist the silicon oxide of the F doping of the ability of deformation, due to oxygen
The fragility of SiClx, the stress therefore produced when cutting easilys lead to it and ruptures, and by increasing
Add the area of the metal level with preferable ductility, reduce the area of silicon oxide with this, thus can drop
The probability ruptured is produced less than wafer when cutting.Further, since Cutting Road is usually provided with test knot
Structure, therefore when carrying out the extension of upper metal layers, need to guarantee not affect the detection welding pad of test structure
Size, if extension oversize, the Cutting Road between chip and chip can be made too narrow, thus
The size making detection welding pad is unsatisfactory for requirement, and then makes the detection of test device by more difficulty.
Embodiment two
Fig. 3 is the sectional view of the seal ring structure of the embodiment of the present invention two, as it is shown on figure 3, with enforcement
Example one is compared, and in the present embodiment, described passivation layer 120 has an opening running through passivation layer 120
121。
After generally the manufacturing process at chip completes, for protection chip in circuit, therefore can be in chip
Surface cover a passivation layer as protective layer, and in Cutting Road 200, be again covered with described protection
Layer, wherein said protective layer is formed in same technical process with the passivation layer 120 in sealing ring.By
In described passivation layer 120 in cutting process, itself easily split, therefore when having described opening 121
In the presence of, the stress that cutting produces is difficult to be delivered to be positioned on the passivation layer of chip surface such that it is able to
Prevent from introducing in the chips crackle.
The opening 121 of described passivation layer 120 can be the most mutual with described metallic channel 111
Staggering, i.e. opening 121 is not in the surface of metallic channel 111.Certainly, the present invention does not limit opening
121 position, it also can realize the purpose of the present invention in the surface of metallic channel 111.
In the present embodiment, described opening 121 is annular opening, surrounds described chip 300.Preferably,
The width of the opening 121 running through described passivation layer 120 is 2～6 μm.
It addition, present invention also offers a kind of employing sealing ring as above to prevent chip in cutting
Time damage method, including: sealing ring as above, the most described sealing are set in the periphery of chip
Ring has more metal layers；And it is provided with on metal level described at least one of which and multiple runs through described gold
Belong to the metallic channel of layer.
Additionally, described sealing ring also includes the passivation layer being positioned at the top of the metal level of top, described
Passivation layer and the protective layer being positioned at described chip surface are formed in same technical process, the most described protection
Layer and described passivation layer can be silicon nitride layer.Preferably, the passivation layer in described sealing ring is opened
If an opening running through described passivation layer.
As it has been described above, in the present invention, by arrange on the metal level in sealing ring multiple metallic channel with
And an opening is set on passivation layer, prevent in wafer dicing process, produce in cut edge
Crack extends to chip, thus the use affecting chip to even result in chip impaired and scrap.Wherein,
Described metallic channel can alleviate the difference of metal level and the coefficient of expansion of inter-metal dielectric layer, reduces stress；
One opening is set on passivation layer, thus the Stress Transfer produced when can avoid cutting is to being positioned at chip list
On the passivating film in face, thus prevent from introducing in the chips crackle.
In this specification, each embodiment uses the mode gone forward one by one to describe, and each embodiment stresses
Being all the difference with other embodiments, between each embodiment, identical similar portion sees mutually i.e.
Can.
Foregoing description is only the description to present pre-ferred embodiments, not any to the scope of the invention
Limit, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification,
Belong to the protection domain of claims.
Claims (18)
1. a sealing ring, described sealing ring includes the more metal layers that stacking is arranged, it is characterised in that:
Multiple metallic channel running through described metal level it is provided with at least one of which metal level.
2. sealing ring as claimed in claim 1, it is characterised in that: described sealing ring also includes being positioned at
Inter-metal dielectric layer between adjacent metal.
3. sealing ring as claimed in claim 2, it is characterised in that: described inter-metal dielectric layer is
Insulating film with low dielectric constant.
4. sealing ring as claimed in claim 3, it is characterised in that: described inter-metal dielectric layer is
The silicon oxide of Fluorin doped.
5. sealing ring as claimed in claim 4, it is characterised in that: the silicon oxide of described Fluorin doped is adopted
Formed by high density plasma CVD technique.
6. sealing ring as claimed in claim 1, it is characterised in that: in described more metal layers,
The width of the metal level being positioned at top is more than the width of other metal level, and described width refers to metal level
It is parallel to the width in chip surface direction.
7. sealing ring as claimed in claim 1, it is characterised in that: described sealing ring also includes being positioned at
Passivation layer on the metal level of top in more metal layers.
8. sealing ring as claimed in claim 7, it is characterised in that: the material of described passivation layer is nitrogen
SiClx.
9. sealing ring as claimed in claim 7, it is characterised in that: offer one on described passivation layer
Run through the opening of described passivation layer.
10. sealing ring as claimed in claim 9, it is characterised in that: described opening is annular opening
And surround described chip.
11. sealing rings as claimed in claim 9, it is characterised in that: the width of described opening is
2～6 μm.
12. sealing rings as claimed in claim 1, it is characterised in that: described metal level is copper or aluminum.
13. sealing rings as claimed in claim 1, it is characterised in that: the cross section shape of described metallic channel
Shape is square.
14. sealing rings as claimed in claim 13, it is characterised in that: the length of side of described metallic channel
It is 1 μm～2 μm.
15. 1 kinds use the claim 1 14 sealing ring as described in one of them prevent chip in
The method of damage during cutting, it is characterised in that:
Arrange described sealing ring in the periphery of described chip, described sealing ring includes more metal layers；
Multiple metallic channel running through described metal level is set at least one of which metal level.
16. prevent chip method of damage when cutting as claimed in claim 15, and its feature exists
The passivation layer on the metal level of top is also included being positioned in more metal layers in: described sealing ring.
17. prevent chip method of damage when cutting as claimed in claim 16, and its feature exists
In: on described passivation layer, offer an opening running through described passivation layer.
18. prevent chip method of damage when cutting as claimed in claim 17, and its feature exists
In: the width of the opening of described passivation layer is 2 μm～6 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596451.5A CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596451.5A CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
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| Publication Number | Publication Date |
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| CN105977226A true CN105977226A (en) | 2016-09-28 |
| CN105977226B CN105977226B (en) | 2019-07-23 |
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| CN201610596451.5A Active CN105977226B (en) | 2016-07-27 | 2016-07-27 | Sealing ring and the method for preventing chip from damaging when cutting |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878378A (en) * | 2017-05-11 | 2018-11-23 | 台湾积体电路制造股份有限公司 | Three-dimensional integrated circuit structure and its manufacturing method |
| CN109920756A (en) * | 2019-03-20 | 2019-06-21 | 德淮半导体有限公司 | Chip sealing ring and forming method thereof |
| WO2022227346A1 (en) * | 2021-04-30 | 2022-11-03 | 深圳市汇顶科技股份有限公司 | Capacitance sensor and manufacturing method therefor |
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| CN1770432A (en) * | 2004-09-13 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Seal ring structure for integrated circuit chips |
| CN1753169A (en) * | 2004-09-24 | 2006-03-29 | 松下电器产业株式会社 | Electronic device and method for fabricating the same |
| CN1988155A (en) * | 2005-12-22 | 2007-06-27 | 中芯国际集成电路制造(上海)有限公司 | Seal ring structure with incomplete contact through hole stack |
| CN101615598A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | The protection sealing ring of the stress that is used to prevent that die separation from causing |
| CN101950743A (en) * | 2009-07-08 | 2011-01-19 | Lsi公司 | To the inhibition of breaking in the integrated circuit of cutting |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878378A (en) * | 2017-05-11 | 2018-11-23 | 台湾积体电路制造股份有限公司 | Three-dimensional integrated circuit structure and its manufacturing method |
| CN109920756A (en) * | 2019-03-20 | 2019-06-21 | 德淮半导体有限公司 | Chip sealing ring and forming method thereof |
| WO2022227346A1 (en) * | 2021-04-30 | 2022-11-03 | 深圳市汇顶科技股份有限公司 | Capacitance sensor and manufacturing method therefor |
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