CN105489649B - Improve the method for termination environment low breakdown voltage in groove-type power device - Google Patents
Improve the method for termination environment low breakdown voltage in groove-type power device Download PDFInfo
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- CN105489649B CN105489649B CN201410478892.6A CN201410478892A CN105489649B CN 105489649 B CN105489649 B CN 105489649B CN 201410478892 A CN201410478892 A CN 201410478892A CN 105489649 B CN105489649 B CN 105489649B
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Abstract
The present invention relates to a kind of MOSFET semiconductor devices for power conversion, the groove power semiconductor device with preferable non-clamper perception switching ability is intended to provide, improve groove power semiconductor device in the low avalanche breakdown ability of termination environment and the method for preparing the device is provided.Step etching terminates groove and active groove, shields the step of terminating groove, being again carried out etching after preparing the termination groove with desired depth value until deepening active groove to expected depth.
Description
Technical field
The present invention relates to a kind of MOSFET semiconductor devices for power conversion, and more precisely, the present invention is directed to carry
For having the groove power semiconductor device of preferable non-clamper perception switching ability, improve groove power semiconductor device
Part termination environment low avalanche breakdown ability and the method for preparing the device is provided.
Background technology
In power conversion apparatus, based on the considerations of transistor unit density and other various advantages, grid can be formed
Among the groove extended downwardly from the surface of bulk silicon substrate, typical example is exactly grooved MOSFET, other examples
The insulated gate bipolar transistor of plough groove type is such as further included, there are one public features for they, are exactly all to have including all kinds of
The groove of various functions, but for the characteristic of device self structure, sometimes, the electric field strength at the channel bottom of termination environment
It shows the maximum field density for device, on the point for being increased to that device enters snowslide in voltage, is avenged in the corner of groove
It collapses breakdown and ionization by collision occurs, it may occur that breakdown generates avalanche current.Avalanche breakdown is generally easy to cause hot carrier's effect,
When puncturing close at grid oxic horizon, an adverse consequences is that hot carrier can be captured and be injected into gate oxidation
Layer, this can damage or be broken grid oxic horizon, induce the long-term integrity problem of power device.In addition, such groove is normal
Often reach the limiting factor of high-breakdown-voltage as device.
If in general, during low current level avalanche breakdown, the obstruction device that breakdown will not be excessive occurs for termination environment
The performance of part, at this time device need not worry trouble free service problem.But once during some special work, such as non-clamper
During perceptual switching, since the electric current of inductance in circuit system will not be mutated, device is caused often to bear some and is compared
Big voltage strength is equivalent to during device is in the horizontal avalanche breakdown event of high current, and the termination environment of limited area is likely to
Safely and effectively processing power loss is will be unable to, because a power device can not possibly cut down the face of the effective transistor unit of device
Long-pending and excessive ad infinitum to termination environment distribution area, and consequence is exactly, the breakdown of termination environment can come as a negative effect
The area of safety operaton (SOA) of device is affected, this is all that our institutes are undesired.The especially gate trench of active area
With the termination gash depth of termination environment it is inconsistent when, a very low level that breakdown voltage is clamped down in termination environment.
Exactly in view of such various difficult problems that the prior art is faced, it is considered herein that necessary limit device
In area of safety operaton SOA and under the conditions of being set in optimal non-clamper perception switch UIS, the electricity for being distributed in device is readjusted
Field intensity makes power conversion apparatus have preferable SOA and good UIS abilities, so the present invention is exactly under the premise of this
Propose every embodiment in subsequent content.
Invention content
In one embodiment, present invention is disclosed a kind of preparation method of groove power semiconductor device, including with
Lower step：One Semiconductor substrate, the epitaxial layer comprising base substrate and above base substrate are provided；Etch epitaxial layer,
For first time etch step, formed active area the first depth of tool active groove with synchronize formed termination environment tool be expected it is deep
The termination groove of degree, the first depth value is smaller than the desired depth value of the termination groove at this time；Then a mask covering is recycled
On termination groove but expose active groove；And continue the step of implementation etches to increase the depth of active groove, it is second
Secondary etch step obtains the active groove of the second depth of expected tool；Wherein the second depth with termination groove desired depth it
Between difference, than the first depth and terminate groove desired depth between difference it is small.
In the step of above method, etching epitaxial layer, first a hard mask layer is set to be covered on Semiconductor substrate
And form opening therein；The size of the opening of active groove is prepared for etching, opening for termination groove is prepared than being used to etch
Mouthful size it is small, make termination groove wider than active groove, and nationality by is formed terminate groove etch rate ratio formed it is active
The etch rate of groove is fast, and the desired depth for making termination groove is deeper than the first depth.
The above method further includes：In active groove, the respective bottom of termination groove and side wall insulation liner layer, and fill
In conductive material to active groove, termination groove；It returns and carves conductive material, only retain active groove, termination groove respectively lower part
Conductive material；Fill insulant is to active groove, termination groove respective top；The insulating materials carved in active groove is returned,
Carved with returning close to a part of insulating materials of active area side in one of termination environment termination groove, at the same retain active groove,
Terminate a dielectric isolation layer of the groove respectively on the conductive material of lower part；In active groove, termination groove, respectively top is naked
Another insulating layer is covered on the side wall of dew, and is refilled with conductive material to active groove, the respective top of termination groove.
The above method further includes：The implantation ion opposite with Semiconductor substrate conduction type is formed to the top of epitaxial layer
One body layer at least about active groove top lateral wall circumference and be subsequently implanted identical with Semiconductor substrate conduction type
Ion forms a top doped layer to the top of body layer.
The above method, fill insulant to active groove after terminating the respective top of groove, terminate ditch in termination environment
A part of the insulating materials of the top filling of slot close to termination environment is blocked by a mask, but terminate the top filling of groove
Insulating materials is but exposed close to another part of active area from the mask, so that the top filling of termination groove is led
Electric material is deviated to active area.
The above method performs in the step of second of etching deepens the depth of active groove, reduces the expection of termination groove
The difference of the second depth that depth and active groove have between the two makes their difference close to 0, for inhibiting in termination environment
One of close active area termination trench bottom corner at the avalanche breakdown that induces.
In another embodiment, the invention discloses a kind of groove power semiconductor device, including：One semiconductor
Substrate, Semiconductor substrate include base substrate and the epitaxial layer above base substrate；In the epitaxial layer of termination environment
First groove and the second groove in the epitaxial layer of active area；The width of second groove is narrower than first groove and second
The depth of groove is not less than the depth of first groove.
Above-mentioned groove power semiconductor device, when avalanche breakdown occurs, avalanche breakdown is happened at active area.
Above-mentioned groove power semiconductor device, such as the second ditch of the first groove of termination groove and such as active groove
Slot has identical depth.
Above-mentioned groove power semiconductor device is attached with one layer than being set on second groove side wall on first groove side wall
Grid oxic horizon will be thick oxide layer.
Above-mentioned groove power semiconductor device, opposite with epitaxial layer conduction type body zone in first groove and
Extend in epitaxial layer between second groove.
Above-mentioned groove power semiconductor device, opposite with body zone conduction type source area in first groove and
Extend between second groove, at the top of body zone.
Above-mentioned groove power semiconductor device, body zone and source area are centered around first groove both sides.
Above-mentioned groove power semiconductor device, body zone and source area are centered around second groove both sides.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Figure 1A~1O is the method flow schematic diagram that the present invention prepares trenched MOSFET devices.
Fig. 2 is the structure diagram for having between active groove and termination groove depth difference.
Specific embodiment
In Figure 1A, in trenched MOSFET devices, Semiconductor substrate includes 100 and of base substrate of a heavy doping
Much lower epitaxial layer 110 is wanted including 100 doping concentration of opposing floor portion substrate, their conductiving doping type is identical, follow-up interior
Hold using N-type epitaxial layer 110 of the epitaxial growth on N+ types substrate 100 and illustrated as demonstration.With one in scheming with opening
The hard mask layer 120 of pattern 101,102 is used as etch mask, implements anisotropic dry etching to epitaxial layer 110, to make
Standby and definition active area or the groove of termination environment, such as Figure 1B, respectively etching formation are extended downwardly from the upper surface of epitaxial layer 110
At least one termination groove 111 and multiple active grooves 112, their bottom are terminated in epitaxial layer 110.In sectional view,
The Local map of the Semiconductor substrate of a separate wafer is illustrated, as demonstration but unrestricted, the termination environment 310 of Semiconductor substrate
With groove 111 is terminated and in the active area 320 of Semiconductor substrate with active groove 112, termination environment 310 is around active
Area 320.Hard mask layer 120 can be single layer structure such as thicker SiO2, the composite construction of multilayer can also be used, is such as included
It is sequentially deposited at the composite construction of silicon oxide-silicon nitride-silica on Semiconductor substrate upper surface from the bottom to top.
The photoresist (not illustrating) being coated on hard mask layer 120 would generally be utilized, by mask after exposed development
Expected channel patterns are transferred in photoresist on plate, and etch hard mask layer 120 using the photoresist with patterns of openings,
Opening 101,102 therein can be formed.Notice that the opening size of opening 101 is bigger than the size of opening 102, the opening of bigger
Width is to etch broader groove in the semiconductor substrate.
In Figure 1B, using hard mask layer 120 as etch mask, the first time etch step of groove is performed.It is etching
In the process, 120 split shed width of hard mask layer is bigger, it is meant that groove is defined wider, dry etching reaction gas
Reactivity particle enters that wide groove is easier, and by contrast, 120 split shed width of hard mask layer is smaller, and groove is determined
Narrowlyer adopted, the reactivity particle of dry etching reaction gas is just more difficult into relatively narrow groove, so different width can be caused
There is difference in the etch rate of degree groove, this is the micro loading effect of plasma etching.Specifically, termination 111 nationality of groove
It is defined by wider opening 101,112 nationality of active groove is defined by relatively narrow opening 102, and termination groove 111 is compared with active groove
112 is wider.At the same time, etching gas for the semiconductor substrate materials below opening 101 when performing etching, etching speed
Rate than the semiconductor substrate materials of the lower section of etching opening 102 rate faster, so forming the etch rate ratio of termination groove 111
The etch rate for forming active groove 112 is fast.
Etching directly forms tool desired depth D1 as a result, when anisotropic dry etch epitaxial layer 110 (such as RIE methods)
Termination groove 111, while also form the active groove 112 of the first depth D2, but the active groove 112 for having depth D2 does not reach also
To final expected depth.In the prior art, an intractable problem is that, the first depth D2 and termination groove 111
Desired depth D1 between there are larger difference T, this difference is enough the breakdown voltage of MOSFET element is allowed to be clamped at terminal
The low breakdown voltage point in area, this will be described in detail in subsequent content.
In Fig. 1 C, a mask 130 is additionally provided, such as photoresist starting of mask 130 is applied to entire Semiconductor substrate
Termination environment 310 and the top of active area 320.Mask 130 is covered on hard mask layer 120, while is also covered in active ditch
On slot 112 and termination groove 111 or it is filled in inside them.After photolithographic exposure develops, it is optionally removed active area 310
Mask 130, mask 130 are only only remained in termination environment 310 at least to cover each termination groove 111.It is active in this way
The active groove 112 in area 320 can be exposed from its mask 130, but the termination groove 111 of termination environment 310 is still covered
Film 130 is covered or is filled.
In Fig. 1 D, second of etch step of groove is performed, continues to implement anisotropic dry etch step.Having
Source region 320 is still using hard mask layer 120 as etch mask, to etch under 112 bottom of active groove of the first depth D2 of tool
110 part of epitaxial layer of side, to increase the depth of active groove 112.And termination environment 310 is in addition to original hard mask layer 120
Outside, a mask 130 has also been additionally introduced as etching shielded layer, and effect is, deepens the same of active groove 112 in etching
When, groove 111 is terminated because the shielding action of mask 130 is without exposed, the epitaxial layer 110 of termination 111 bottom part down of groove
The influence of any etching is not exposed to, any change will not occur for termination 111 original desired depth D1 of groove.During this, add
The etch step of deep active groove 112 stops at active groove 112 and reaches the second depth D'2, this is that active groove 112 is final
Desired depth, one object of the present invention are that, it is expected to reduce the termination desired depth D1 of groove 111 and active groove 112
The differences of the second depth D'2 finally having between the two make the second depth D'2 with terminating the desired depth D1 of groove 111 almost
It is equal, it is furthermore preferred that making the second depth D'2 not less than the desired depth D1 of termination groove 111.Stripping is needed to remove end thereafter
Petiolarea 310 covers the mask 130 of the termination groove 111, and the termination groove 111 that finally obtains, active groove 112 are all to downward
It stretches, until their bottom is all located in epitaxial layer 110, their bottom is substantially flush.
Statement in advance the step of announcement based on Figure 1A~1D of the present invention, is realized and minimizes active groove and termination groove
Between depth difference purpose, spirit of the invention embodied, and subsequently prepares the side of groove MOSFET device
Case is not unique, any one means based on Figure 1A~1D and prepare the invention essence of the method for MOSFET all without departing from this case
God.Although the MOSFET element that (Fig. 1 E~1M) further illustrates a complete structure in subsequent content is how to promote breakdown
Voltage, but the embodiment as just demonstration and is explained, is not construed as limiting.
In Fig. 1 E, after the mask 130 for removing termination environment 310, termination groove 111,112 respective side wall of active groove and bottom
Epitaxial layer 110 all expose.Then such as Fig. 1 F, the side wall of groove 111 and each active groove 112 and bottom are being terminated
A thick dielectric layer 116 is grown, the silicon dioxide layer typically for example grown using hot oxygen technique.As shown in Figure 1 G, thereafter again
Deposition conductive material 140 (polysilicon of such as heavy doping) is covered on hard mask layer 120, and conductive material 140 is also filled out simultaneously
It fills in each termination groove 111, active groove 112, conductive material 140 can for example be formed by chemical vapor deposition CVD
The polysilicon of phosphorus doping in situ.
In Fig. 1 H, the step of carving conductive material 140 is performed back, the conductive material 140 of 120 top of hard mask layer is etched
It removes, while returns quarter and remove in the termination groove 111,112 respective inside of active groove compared with the conductive material on top
140, in the top leaving gap space of each groove 111,112.As shown in fig. 1H, after returning and carving, retain in termination groove 111
The conductive material 140b of lower part and retain the conductive material 140a of lower part among each 112 inside of active groove in portion, lead to
This point can be realized by often performing the polysilicon dry back carving technology of standard.Although termination environment 310 can set one or more
A termination groove 111, for the convenience of narration, shows only innermost one near active area 320 or center wafer
A termination groove 111.
It, will be exhausted by low-pressure chemical vapor deposition LPCVD or plasma enhanced chemical vapor deposition PECVD in Fig. 1 I
Edge material 145 fill each termination groove 111 into Fig. 1 H, 112 top of active groove clearance space in, it is typical to insulate
Such as silica of material 145, insulating materials 145 are also covered in the top of hard mask layer 120 simultaneously.Hereafter it such as Fig. 1 J, needs to remove
(such as CMP methods) hard mask layer 120 and its insulating materials 145 of top are removed, only retains termination groove 111, active groove 112
The insulating materials 145 of respective top filling, while the insulating layer 116 being attached in these groove upper portion side walls originally is fused
In insulating materials 145.It is worth noting that, needing thereafter that insulating materials 145 carve, and need to be coated in half using one
Etch mask 146 above conductor substrate, starting mask 146 cover active area and termination environment.As shown in figure iK, it is patterned
Mask 146, termination groove 111 is covered close to a part for termination environment 310 or Waffer edge side by mask 146, but is terminated
The another part of groove 111 close to active area 320 or center wafer side is exposed from the mask 146, active area 320
It is exposed from mask 146.Using mask 146 as etch mask, to exposed one of termination groove 111 compared with top
Divide insulating materials 145 and etching is implemented to the exposed insulating materials 145 on 112 top of active groove.It terminates on groove 111
The part that the insulating materials 145 of portion's filling is exposed from mask 146 can be etched away, but insulating materials 145 in groove 111
Another part 145b not exposed from mask 146 close to termination environment or Waffer edge side can be remained.
Such as Fig. 1 L, to be returned in the step of carving what is performed to insulating materials 145,145 overwhelming majority of insulating materials is all removed,
But a part is also retained, such as conductive material 140b, 140a in termination groove 111,112 respective lower part of active groove
Top prepares insulating materials 145c, and insulating materials 145c derived from etching insulating material 145 but belongs to its portion being retained
Point, and as dielectric isolation layer.During this, the shape in a part of region of the original insulating materials 145 on 111 top of termination groove
Clearance space is formd into clearance space and on the top of active groove 112 so that the side wall on the top of active groove 112
Be it is exposed, termination 111 top of groove close to the side wall of active area 320 or center wafer be it is exposed, Semiconductor substrate it is upper
Surface is also exposed, but due to remaining the groove in termination groove 111 top close to termination environment or Waffer edge side
Insulating layer 145b on side wall so the side wall that termination groove 111 is covered by insulating layer 145b will not expose, is hereafter needed
It removes and removes mask 146.
In Fig. 1 M, one layer of densification is first generated on the exposed upper surface of Semiconductor substrate namely the upper surface of epitaxial layer 110
Insulating layer 118, insulating layer 118 is also covered in simultaneously on the exposed side wall in termination groove 111,112 respective top of active groove.
Wherein, side wall of the insulating layer 118 than groove (111,112) lower part of liner and bottom on the side wall on groove (111,112) top
The insulating layer 116 of upper attachment is much thinner.Hereafter, another secondary conductive material 150 (such as polycrystalline of phosphorus doping in situ is deposited again
Silicon), it is covered in the top of the insulating layer 118 on Semiconductor substrate upper surface and is filled in termination groove 111, active groove
In the clearance space on 112 respective tops.Then it performs returning for conductive material 150 and carves step, on Semiconductor substrate upper surface
The conductive material 150 that covers of the top of insulating layer 118 return quarter and get rid of, while retain respectively：In 112 upper space of active groove
The conductive material 150a of filling, the interior conductive material 150b filled of 111 upper space of termination groove.At this time due to existing than insulation
The much thick insulating layer 145b of layer 118, it is into active area 320 or chip in termination groove 111 to lead to conductive material 150b
Heart offset.At this point, the insulating layer 118 above Semiconductor substrate upper surface exposes, so-called Semiconductor substrate upper table here
Insulating layer 118 above face refers to the part that insulating layer 118 is overlapped on Semiconductor substrate upper surface, without being attached to end
Connect groove 111, the part insulating layer 118 in 112 upper portion side wall of active groove.
As shown in Fig. 1 N, by comprehensive ion implanting (blanket implant), body layer 160 and top are successively formed
Doped layer 170, source area/source doping region of the top doped layer 170 as mosfet transistor unit.Body layer 160 is led
Electric type is opposite with Semiconductor substrate (for p-type), and the conduction type of top doped layer 170 is identical with Semiconductor substrate, but adulterates
Concentration is more than epitaxial layer 110, is N+ types.Body layer 160 is located at the top of epitaxial layer 110, at least about these grooves (111,
112) around compared with the side wall on top, top doped layer 170 is located at the top of body layer 160 and positioned at the upper table of epitaxial layer 110
Near face, also around around side wall of these grooves compared with top, but much lighter than body layer 160.In splitting bar device
In part, the ion implanting depth of body layer 160 will meet some requirements：Body layer 160 is with epitaxial layer 110 in active groove
112nd, terminate groove 111 near interface position, outline be higher than conductive material 150a, 150b bottom surfaces position, so as to
Ditch can be established in body layer 160 along the inversion layer that the side wall of active groove 112 or termination groove 111 is formed in vertical direction
Road.
In Fig. 1 O, insulating passivation layer 190 (such as a low temperature oxide LTO and/or the silica glass containing boric acid are deposited
BPSG), it is covered on Semiconductor substrate upper surface, it has also merged original insulating layer on Semiconductor substrate upper surface
118.Insulating passivation layer 190 is also covered in the top of insulating materials 145b, conductive material 150b and 150a simultaneously.It is blunt to prepare insulation
After changing layer 190, additional one photoresist layer of spin coating, and form some of which and open again above insulating passivation layer 190 is needed
Mouth pattern by the use of this photoresist layer as contact hole etching mask, after appropriate anisotropic dry etch, is formed
Several contact holes 303 through 190 thickness of insulating passivation layer.
Contact hole 303 is extended downwardly into the body layer 160 of active area 320, also extends through the top doped layer of active area 320
170.In some embodiments, some contact holes 303 extend downwardly into the body layer 160 between two neighboring active groove 112
Interior and some contact holes 303 extend downwardly into an outermost active groove in multiple active grooves 112 arranged side by side
In body layer 160 between 112 and termination groove 111.In some optional embodiments, termination groove 111 can be closed
Ring-shaped groove, this outermost active groove 112 are exactly terminate groove 111 one that is parallel to active groove 112 in fact
An active groove near point.Pay attention to the body contacts of the injection heavy doping in the body layer 160 of 303 bottom periphery of contact hole
The step of area's (P+ type), is not shown in figure.
In Fig. 1 O, it can be deposited in the bottom of each contact hole 303 and side wall and on the upper surface of insulating passivation layer 190
Then one barrier metal layer refills metal material (such as tungsten) in each contact hole 303, the potential barrier gold in contact hole 303
Belong to layer and metal plug or metal joint is collectively formed in metal material.
Then, then the top that a metal layer at top is covered in entire insulating passivation layer 190 is prepared, if insulating passivation layer
190 upper surfaces have been previously deposited barrier metal layer, then metal layer at top is covered on barrier metal layer.Later to it
Implement to pattern, divide metal layer at top and barrier metal layer, at least prepare a top metal electrode 220.Top metal
Electrode 220 (as source electrode) is at least overlapped on part active area 320.Metal plug in contact hole 303 will be active
The body layer 160 in area 320,170 short circuit of top doped layer, and they are electrically connected to top metal electrode 220.Optional
In embodiment, in the dimension not illustrated, the active groove 112 of strip can be with termination groove 111 perpendicular to active ditch
The part connection of slot 112, so as to the conductive material 140a of 112 lower part of active groove and the conduction material of 111 lower part of termination groove
Expect 140b interconnection, conductive material 140a, 140b are electrically connected to top metal electrode 220, in source potential.In addition, not
In the dimension illustrated, the conductive material 150a on 112 top of active groove and the conductive material of 111 top of termination groove filling
150b is interconnected, while on the conductive material being connected in the grid pickup groove not illustrated, and is directed at and contacts grid pickup
Conductive material 150a, 150b can be exported to 190 top one of insulating passivation layer by the metal plug of the conductive material in groove
On gate metal electrode.In addition, a bottom metal electrode not illustrated being covered on 100 bottom surface of base substrate is as leakage
Pole electrode.
FET unit or transistor unit cell are integrated in active area 320, the conductive material of 112 lower part of active groove
Dhield grids of the 140a as MOS transistor unit, the control gate of the conductive material 150a on top as MOS transistor unit
Pole, control grid 150a are overlapped on dhield grid 140a, and by the dielectric isolation layer 145c between them, the rwo is electric each other
Insulation.Active groove 112 or termination groove 111 in, as grid oxic horizon insulating layer 118 (or referred to as second insulation
Layer) it is thin than insulating layer 116 (or referred to as first insulating layer) adhered on groove 111, the side wall of 112 lower parts or bottom.
More special, a part for the termination original insulating materials 145 in 111 top of groove is etched away, and is then filled out
The conductive material 150b filled also serves as a gate electrode, can be along 111 top of termination groove close to active area 320 or chip
The side wall of center side builds vertical channel region, and to be attached to the insulating layer on the side wall of this side in body layer 160
118 are used as grid oxic horizon.In addition, insulating layer 145b of 111 top of termination groove on the side wall of 310 side of termination area
(or referred to as third insulating layer) is much thicker than insulating layer 116,118, and insulating layer 145b is exactly that insulating materials 145 is filled in fact
That part for not being etched and retaining on 111 top of termination groove.Gate electrode 150b and the bucking electrode 140b of lower section lead to
The dielectric isolation layer 145c crossed between them is electrically insulated from each other.
Symmetrical center line AAs of the gate electrode 150b in its width direction, with termination groove 111 in the direction of the width
Symmetrical center line BB is simultaneously misaligned, and center line AA is to distance of the groove 111 close to 310 side side wall of termination environment is terminated, than arriving
It is big close to the distance of 320 side side wall of active area to terminate groove 111.In view of the symmetrical center line AA of gate electrode 150b is to active
Area 320 or center wafer offset by some distances, it is believed that gate electrode 150b is with asymmetrical on 111 top of termination groove
Mode is set, and is offset by a little gently towards active area 320 or center wafer.
The structure of Fig. 2 and Fig. 1 M is essentially identical, in addition between the depth of active groove 112 and the depth of termination groove 111
Difference is larger, this is frequently in problems of the prior art (i.e. the result of Figure 1B).Default deeper termination groove 111
The difference that depth value subtracts the depth value of active groove 112 is T, is carried out between the source electrode and drain electrode of Trenched MOSFET elements
When breakdown voltage emulates, whens T value differences, embodies the different pressure-resistant performance of device：T values are bigger, the breakdown voltage resistant ability of device
Smaller, vice versa, and T values are smaller, and the breakdown voltage resistant ability of device is bigger.
When T values are larger, the breakdown voltage of device is clamped down on by termination environment compared with low breakdown voltage.Such as MOSFET element
During operating in non-clamped Inductive switch UIS (Un-damped Inductive Switching) handover event, groove is terminated
111 bottom corners position is avalanche breakdown weakness, it is easy to avalanche breakdown is induced at the bottom corners of termination groove 111,
The bottom corners of 320 side of close active area of groove 111 are especially terminated, ionization by collision will occur in avalanche breakdown process,
Generate avalanche current.Avalanche breakdown is generally easy to cause hot carrier's effect, when close to insulating layer 116 (a such as oxide layer)
When vicinity punctures, an adverse consequences is that hot carrier can be captured and be injected into insulating layer 116, so as to damaging or
Grid oxic horizon is broken, induces the long-term integrity problem of power device.According to spirit of the invention, T values are reduced, in termination environment 310
Electric field strength and crowding at the bottom corners of the termination groove 111 of active area 320 is retarded, effectively inhibits
The probability of avalanche breakdown occurs for 310 breakdown weak points of termination environment, improves the breakdown voltage of termination environment and the robustness of device, such as
Breakdown voltage (BVDSS) is greatly improved between embodying drain-source of the MOSFET element in gate-source short circuit.
More than, by explanation and attached drawing, give the exemplary embodiments of the specific structure of specific embodiment, foregoing invention
Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading
State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention
True intention and range whole variations and modifications.In Claims scope the range of any and all equivalence with it is interior
Hold, be all considered as still belonging to the intent and scope of the invention.
Claims (6)
1. a kind of preparation method of groove power semiconductor device, which is characterized in that include the following steps：
Semi-conductive substrate, the epitaxial layer comprising base substrate and above base substrate are provided；
Epitaxial layer is etched, the end of the active groove for forming the first depth of tool of active area and the tool desired depth for forming termination environment
Groove is connect, the first depth is smaller than the desired depth value for terminating groove；
It is covered on termination groove using a mask but exposes active groove；
The step of continuing to implement etching obtains the active groove of the second depth of expected tool to increase the depth of active groove；
Difference between wherein the second depth and the desired depth for terminating groove, than the first depth and the desired depth of termination groove
Between difference it is small.
2. the method as described in claim 1, which is characterized in that in the step of etching epitaxial layer, a hard mask is first set
Layer is covered on Semiconductor substrate and forms opening therein；
The size of the opening of active groove is prepared for etching, the size than being used to etch the opening for preparing termination groove is small,
Make termination groove wider than active groove, and nationality terminates etch rate of the etch rate than forming active groove of groove by being formed
Soon, the desired depth for making termination groove is deeper than the first depth.
3. the method as described in claim 1, which is characterized in that further include：Active groove, the respective bottom of termination groove and
Side wall insulation liner layer, and fill in conductive material to active groove, termination groove；
Return and carve conductive material, only retain active groove, the respective lower part of termination groove conductive material；
Fill insulant is to active groove, termination groove respective top；
It returns the insulating materials carved in active groove and returns and carve in the termination groove of termination environment close to the part insulation of active area side
Material, while retain active groove, termination groove a respectively dielectric isolation layer on the conductive material of lower part；
Another insulating layer is covered, and be refilled with conduction material on active groove, termination the groove respectively exposed side wall in top
Expect to active groove, the respective top of termination groove.
4. method as claimed in claim 3, which is characterized in that further include：Implantation is opposite with Semiconductor substrate conduction type
Ion to the top of epitaxial layer, formed a body layer at least about active groove top lateral wall circumference and be subsequently implanted with
The identical ion of Semiconductor substrate conduction type forms a top doped layer to the top of body layer.
5. method as claimed in claim 3, which is characterized in that fill insulant to active groove, termination groove are respective
After top, a part of the insulating materials close to termination environment for terminating the top filling of groove is blocked, but close by a mask
Another part of active area is exposed from the mask, so as to make the conductive material that termination groove top is filled inclined to active area
It moves.
6. the method as described in claim 1, which is characterized in that the desired depth and active groove for reducing termination groove finally have
The difference of the second depth having between the two makes their difference close to 0, to inhibit the snow induced at termination trench bottom corner
Collapse breakdown.
Priority Applications (1)
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| CN111755526A (en) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | Trench MOS device and preparation method |
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| CN102246306A (en) * | 2008-12-08 | 2011-11-16 | 飞兆半导体公司 | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
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