CN105489649A - Method for improving terminal area low breakdown voltage in groove type power device - Google Patents
Method for improving terminal area low breakdown voltage in groove type power device Download PDFInfo
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- CN105489649A CN105489649A CN201410478892.6A CN201410478892A CN105489649A CN 105489649 A CN105489649 A CN 105489649A CN 201410478892 A CN201410478892 A CN 201410478892A CN 105489649 A CN105489649 A CN 105489649A
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Abstract
The invention relates to an MOSFET semiconductor device for power conversion, and is aimed to provide a groove type power semiconductor device which has the excellent unclamping inductive switch handover ability and can improve the low avalanche breakdown ability of a terminal area of the groove type power semiconductor device, and provides a method for preparing the groove type power semiconductor device. The method includes: etching end-jointed grooves and active grooves; preparing end-jointed grooves having an expected depth value, and then shielding the end-jointed grooves; performing again an etching step until the active grooves are deepened to the expected depth.
Description
Technical field
The present invention relates to a kind of MOSFET semiconductor device for power transfer, more precisely, the present invention aims to provide the groove power semiconductor device with better non-clamper perception switching over ability, and improving groove power semiconductor device in the low avalanche breakdown ability of termination environment provides the method for this device of preparation.
Background technology
In power conversion apparatus, based on the consideration of transistor unit density with other various advantages, grid can be formed in from the surface of bulk silicon substrate among the groove of downward-extension, typical example is exactly grooved MOSFET, other the insulated gate bipolar transistor etc. such as also comprising plough groove type, they have a public feature, be exactly all comprise all kinds of groove with various function, but for the characteristic of device self structure, some time, the electric field strength at the channel bottom place of termination environment demonstrates the maximum field density into device, being elevated to device at voltage enters on the point of snowslide, there is avalanche breakdown in the bight of groove and occur ionization by collision, generation avalanche current can be punctured.Avalanche breakdown is generally easy causes hot carrier's effect, when puncturing close to grid oxic horizon place, adverse consequences is that hot carrier can be captured and is injected into grid oxic horizon, and this grid oxic horizon that can damage or rupture, brings out the integrity problem that power device is long-term.In addition, such groove usually becomes the limiting factor that device reaches high-breakdown-voltage.
Generally speaking, if during low current level avalanche breakdown, termination environment punctures the performance of obstruction device that can not be excessive, and now device is without the need to worrying trouble free service problem.But once at some special duration of works, such as, during non-clamper perception switching over, because the electric current of inductance in Circuits System can not suddenly change, cause device often will bear some larger voltage strengths, be equivalent to during device is in high levels of current avalanche breakdown event, the termination environment of limited area probably cannot processing power loss safely and effectively, because a power device can not be cut down the area of the effective transistor unit of device and ad infinitum distribute excessive area to termination environment, and consequence is exactly, puncturing of termination environment can as a negative effect have impact on the area of safety operaton (SOA) of device, this is all that we undesirably occur.Especially the gate trench of active area and the termination gash depth of termination environment inconsistent time, the level that of puncture voltage being clamped down in termination environment is very low.
Just in view of these various difficult problems that prior art faces, it is considered herein that necessary device is limited to area of safety operaton SOA and is set in optimum non-clamper perception switch UIS condition under, readjust the electric field strength being distributed in device, power conversion apparatus is made to possess preferably SOA and good UIS ability, so the present invention is exactly the every embodiment proposed under this prerequisite in subsequent content.
Summary of the invention
In one embodiment, present invention is disclosed a kind of preparation method of groove power semiconductor device, comprise the following steps: a Semiconductor substrate is provided, comprise base substrate and be positioned at the epitaxial loayer above base substrate; Etching epitaxial loayer, is first time etch step, is formed with the active groove of tool first degree of depth in source region, and the synchronous termination groove forming the tool desired depth of termination environment, and now the first depth value is less than the desired depth value of this termination groove; And then utilize a mask to cover on termination groove but expose active groove; And the step continuing to implement to etch is to increase the degree of depth of active groove, is second time etch step, obtain the active groove of tool second degree of depth of expection; Difference between the desired depth of wherein second degree of depth and termination groove is less than the difference between first degree of depth and the desired depth of termination groove.
Said method, in the step of etching epitaxial loayer, first arranges a hard mask layer and to cover on Semiconductor substrate and to form opening wherein; For etching the size of the opening preparing active groove, less than the size of the opening for etching preparation termination groove, make termination groove wider than active groove, and nationality is faster than the etch rate forming active groove by the etch rate forming termination groove, makes the desired depth of termination groove darker than first degree of depth.
Said method, also comprises: at the respective bottom of active groove, termination groove and sidewall insulation liner layer, and filled conductive material is in active groove, termination groove; Return and carve electric conducting material, only retain the electric conducting material of active groove, termination groove bottom separately; Fill insulant is to active groove, termination groove top separately; Return the insulating material carved in active groove, and return carve termination environment a termination groove in a part of insulating material near side, active area, a dielectric isolation layer on the electric conducting material simultaneously retaining active groove, termination groove bottom separately; Active groove, the termination groove sidewall that top is exposed separately covers another insulating barrier, and again filled conductive material to active groove, termination groove top separately.
Said method, also comprise: implant the top of the ion contrary with Semiconductor substrate conduction type to epitaxial loayer, form the lateral wall circumference that a body layer is at least centered around active groove top, implant the ion identical with Semiconductor substrate conduction type subsequently to the top of body layer, form a top doped layer.
Said method, after fill insulant to active groove, termination groove top separately, the part of insulating material near termination environment that in termination environment, the top of termination groove is filled is blocked by a mask, but insulating material another part near active area that the top of termination groove is filled is come out from this mask, offsets to active area with the electric conducting material making termination groove top fill.
Said method, performing second time etching deepens in the step of the degree of depth of active groove, second degree of depth difference between the two that the desired depth of reduction termination groove and active groove have, make their difference close to 0, for the avalanche breakdown suppressing a termination trench bottom corner place of the close active area in termination environment to bring out.
In another embodiment, the invention discloses a kind of groove power semiconductor device, comprising: a Semiconductor substrate, Semiconductor substrate comprises base substrate and is positioned at the epitaxial loayer above base substrate; Second groove of the first groove being arranged in the epitaxial loayer of termination environment and the epitaxial loayer being arranged in active area; The width of the second groove and the degree of depth of second groove narrower than the first groove is not less than the degree of depth of the first groove.
Above-mentioned groove power semiconductor device, when there is avalanche breakdown, avalanche breakdown occurs in active area.
Above-mentioned groove power semiconductor device, the first groove of such as termination groove and the second groove of such as active groove have the identical degree of depth.
Above-mentioned groove power semiconductor device, the first trenched side-wall is attached with the oxide layer that one deck is thicker than the grid oxic horizon that the second trenched side-wall is arranged.
Above-mentioned groove power semiconductor device, extends in the epitaxial loayer of a body zone contrary with epitaxial loayer conduction type between the first groove and the second groove.
Above-mentioned groove power semiconductor device, a source area contrary with body zone conduction type extends between the first groove and the second groove, is positioned at body zone top.
Above-mentioned groove power semiconductor device, body zone and source area are centered around the first groove both sides.
Above-mentioned groove power semiconductor device, body zone and source area are centered around the second groove both sides.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Figure 1A ~ 1O is the method flow schematic diagram that the present invention prepares trenched MOSFET devices.
Fig. 2 is the structural representation between active groove and termination groove with degree of depth difference.
Embodiment
In Figure 1A, in trenched MOSFET devices, Semiconductor substrate comprises a heavily doped base substrate 100, with comprise opposing floor portion substrate 100 doping content and want much lower epitaxial loayer 110, their conductiving doping type is identical, and subsequent content is exemplarily described with the N-type epitaxial loayer 110 of epitaxial growth on N+ type substrate 100.Using a hard mask layer 120 with patterns of openings 101,102 in scheming as etch mask, anisotropic dry etching is implemented to epitaxial loayer 110, prepare and define the groove of active area or termination environment, as Figure 1B, etching forms at least one termination groove 111 from from the upper surface of epitaxial loayer 110 to downward-extension and multiple active groove 112 respectively, and their bottom terminates in epitaxial loayer 110.In profile, illustrate the Local map of the Semiconductor substrate of an independent wafer, exemplarily but unrestricted, the termination environment 310 of Semiconductor substrate has termination groove 111 and have active groove 112 in the active area 320 of Semiconductor substrate, and termination environment 310 is round active area 320.Hard mask layer 120 can be that single layer structure is as thicker SiO
2, also can adopt the composite construction of multilayer, as comprised the composite construction of the silicon oxide-silicon nitride-silicon dioxide be deposited on successively from the bottom to top on Semiconductor substrate upper surface.
Usually the photoresist (not illustrating) be coated on hard mask layer 120 can be utilized; after exposure imaging, the channel patterns that mask plate is expected is transferred in photoresist; and utilize the photoresist etching hard mask layer 120 with patterns of openings, just can form opening 101,102 wherein.Notice that the opening size of opening 101 is larger than the size of opening 102, larger A/F is to etch wider groove in the semiconductor substrate.
In Figure 1B, using hard mask layer 120 as etch mask, perform the first time etch step of groove.In etching process, hard mask layer 120 split shed width is larger, mean that groove is defined wider, it is easier that the reactivity particle of dry etching reacting gas enters wide groove, and by contrast, hard mask layer 120 split shed width is less, groove is defined narrower, it is more difficult that the reactivity particle of dry etching reacting gas enters narrower groove, so the etch rate of different in width groove can be caused to occur difference, this is the micro loading effect of plasma etching.Specifically, termination groove 111 nationality is defined by wider opening 101, and active groove 112 nationality is defined by narrower opening 102, and termination groove 111 is wider than active groove 112.Meanwhile, etching gas is when etching for the semiconductor substrate materials below opening 101, its etch rate is faster than the speed of the semiconductor substrate materials below etching opening 102, so the etch rate forming termination groove 111 is faster than the etch rate forming active groove 112.
Etching result is, when anisotropic dry etch epitaxial loayer 110 (as RIE method), the termination groove 111 of direct formation tool desired depth D1, also forms the active groove 112 of the first degree of depth D2 simultaneously, but the active groove 112 of tool degree of depth D2 does not also reach the degree of depth of final expection.In the prior art, a thorny difficult problem is just, there is larger difference T between the desired depth D1 of this first degree of depth D2 and termination groove 111, this difference is enough to allow the puncture voltage of MOSFET element be clamped at the low breakdown voltage point of termination environment, and this will introduce in detail in subsequent content.
In Fig. 1 C, additionally provide a mask 130, above the termination environment 310 that mask 130 is applied to whole Semiconductor substrate as photoresist is initial and active area 320.Mask 130 covers on hard mask layer 120, also covers on active groove 112 and termination groove 111 simultaneously or is filled in their inside.After photolithographic exposure development, optionally remove the mask 130 of active area 310, mask 130 is only retained in termination environment 310 to cover to each termination groove 111 of major general.The active groove 112 of such active area 320 just can be out exposed from its mask 130, but the termination groove 111 of termination environment 310 is still covered by mask 130 or fills.
In Fig. 1 D, perform the second time etch step of groove, continue to implement anisotropic dry etch step.In active area 320 still using hard mask layer 120 as etch mask, etch epitaxial loayer 110 part of active groove 112 bottom part down of tool first degree of depth D2, to increase the degree of depth of active groove 112.And termination environment 310 is except original hard mask layer 120, additionally introduce a mask 130 in addition as etching screen, effect is, while etching deepens active groove 112, termination groove 111 does not expose because of the shielding action of mask 130, the epitaxial loayer 110 of termination groove 111 bottom part down can not suffer the impact of any etching, and any change can not occur the original desired depth D1 of termination groove 111.During this, the etch step of deepening active groove 112 stops at active groove 112 and reaches the second degree of depth D'2, this is the final desired depth of active groove 112, one object of the present invention is just, expect to reduce the second degree of depth D'2 difference between the two that the desired depth D1 of termination groove 111 and active groove 112 finally have, make the desired depth D1 of the second degree of depth D'2 and termination groove 111 almost equal, preferred, make the second degree of depth D'2 be not less than the desired depth D1 of termination groove 111.Thereafter need to peel off and remove the mask 130 that termination environment 310 covers this termination groove 111, the termination groove 111 finally obtained, active groove 112 are all to downward-extension, until their bottom is all positioned at epitaxial loayer 110, their bottom is substantially flush.
Leading statement, based on the step that Figure 1A ~ 1D of the present invention discloses, achieve the object minimizing degree of depth difference between active groove and termination groove, invention spirit of the present invention is embodied, it is follow-up, and to prepare the scheme of groove MOSFET device unique, and any one means based on Figure 1A ~ 1D and the method for preparing MOSFET all do not depart from the invention spirit of this case.Although in subsequent content, (Fig. 1 E ~ 1M) further illustrates the MOSFET element of a complete structure is how to promote puncture voltage, this execution mode is as just demonstration and explain, is not construed as limiting.
In Fig. 1 E, after peeling off the mask 130 of termination environment 310, the epitaxial loayer 110 of the respective sidewall of termination groove 111, active groove 112 and bottom is all out exposed.Then as Fig. 1 F, grow a thick dielectric layer 116 at the sidewall of termination groove 111 and each active groove 112 and bottom, typically such as utilize the silicon dioxide layer that hot oxygen technique grows.As shown in Figure 1 G, thereafter deposits conductive material 140 (as heavily doped polysilicon) covers on hard mask layer 120 again, electric conducting material 140 is also filled in each termination groove 111, active groove 112 simultaneously, and electric conducting material 140 for example can form the polysilicon of original position phosphorus doping by chemical vapour deposition (CVD) CVD.
In Fig. 1 H, perform back the step of carving electric conducting material 140, electric conducting material 140 etching above hard mask layer 120 is removed, return the electric conducting material 140 carved and remove compared with top in this termination groove 111, the respective inside of active groove 112, in the leaving gap space, top of each groove 111,112 simultaneously.As shown in fig. 1h, after returning and carving, retain the electric conducting material 140b compared with bottom in termination groove 111 inside, and retain the electric conducting material 140a compared with bottom among each active groove 112 inside, the polysilicon dry back carving technology of usual operative norm can realize this point.Although termination environment 310 can arrange one or more termination groove 111, in order to the convenience described, show only a termination groove 111 of the inner side near active area 320 or center wafer.
In Fig. 1 I, by low-pressure chemical vapor deposition LPCVD or plasma enhanced chemical vapor deposition PECVD, insulating material 145 is filled in the clearance space on each termination groove 111 in Fig. 1 H, active groove 112 top, typical insulating material 145 is as silica, and insulating material 145 also covers the top of hard mask layer 120 simultaneously.After this as Fig. 1 J, need the insulating material 145 removing (as CMP method) hard mask layer 120 and top thereof, the only insulating material 145 of reservation termination groove 111, active groove 112 respective top filling, the insulating barrier 116 be simultaneously originally attached in these groove upper portion side wall is merged in insulating material 145.It should be noted that and need thereafter to carry out back carving to insulating material 145, and need employing one to be coated in the etch mask 146 of semiconductor substrate, initial mask 146 covers active area and termination environment.As shown in figure ik, its mask 146 of patterning, the part of termination groove 111 near termination environment 310 or Waffer edge side is covered by mask 146, but termination groove 111 another part near active area 320 or center wafer side comes out from this mask 146, also comes out in active area 320 from mask 146.Using mask 146 as etch mask, compared with exposed a part of insulating material 145 out on top with to the exposed insulating material 145 out on active groove 112 top, etching is implemented to termination groove 111.The part that the insulating material 145 that termination groove 111 top is filled exposes from mask 146 can be etched away, but in groove 111, insulating material 145 can remain near another part 145b do not exposed from mask 146 of termination environment or Waffer edge side.
As Fig. 1 L, return in the step of carving what perform insulating material 145, insulating material 145 overwhelming majority is all removed, but a part is also retained, such as above electric conducting material 140b, 140a of termination groove 111, the respective bottom of active groove 112, prepare insulating material 145c, namely insulating material 145c comes from etching insulating material 145 but belongs to it and be retained the part of getting off, and as dielectric isolation layer.During this, clearance space is defined in a part of region of the original insulating material 145 on termination groove 111 top, clearance space is defined with the top at active groove 112, the sidewall on the top of active groove 112 is made to be exposed, termination groove 111 top is exposed near the sidewall of active area 320 or center wafer, the upper surface of Semiconductor substrate is also exposed, but owing to remaining the insulating barrier 145b of this groove on the sidewall of termination environment or Waffer edge side in termination groove 111 top, so termination groove 111 can not be out exposed by the sidewall that insulating barrier 145b covers, after this stripping is needed to remove mask 146.
In Fig. 1 M, first at the upper surface that Semiconductor substrate is exposed, the upper surface of also i.e. epitaxial loayer 110 generates the insulating barrier 118 of one deck densification, insulating barrier 118 also covers on termination groove 111, active groove 112 sidewall that top is exposed separately simultaneously.Wherein, on the sidewall on groove (111,112) top, the insulating barrier 118 of liner wants Bao get Duo than the insulating barrier 116 that the sidewall of groove (111,112) bottom and bottom adhere to.After this, again deposit another electric conducting material 150 (such as the polysilicon of original position phosphorus doping), cover the top of the insulating barrier 118 on Semiconductor substrate upper surface, and be filled in the clearance space on termination groove 111, the respective top of active groove 112.Then perform returning of electric conducting material 150 and carve step, the electric conducting material covered above insulating barrier 118 on Semiconductor substrate upper surface is got rid of 150 times quarters, retain respectively: the electric conducting material 150a filled in active groove 112 upper space, the electric conducting material 150b filled in termination groove 111 upper space simultaneously.Now owing to there is much thicker than insulating barrier 118 insulating barrier 145b, cause electric conducting material 150b in termination groove 111 to active area 320 or center wafer skew.Now, insulating barrier 118 above Semiconductor substrate upper surface is out exposed, here the insulating barrier 118 above so-called Semiconductor substrate upper surface refers to that insulating barrier 118 overlaps on the part on Semiconductor substrate upper surface, instead of is attached to the part insulating barrier 118 in termination groove 111, active groove 112 upper portion side wall.
As shown in Fig. 1 N, by comprehensive ion implantation (blanketimplant), successively form body layer 160 and top doped layer 170, top doped layer 170 is as the source area/source doping region of mosfet transistor unit.The conduction type of body layer 160 is contrary with Semiconductor substrate (for P type), and the conduction type of top doped layer 170 is identical with Semiconductor substrate, but doping content is greater than epitaxial loayer 110, is N+ type.Body layer 160 is positioned at the top of epitaxial loayer 110, at least be centered around these grooves (111,112) compared with around the sidewall on top, top doped layer 170 be positioned at body layer 160 top and near the upper surface being positioned at epitaxial loayer 110, it is also centered around these grooves compared with around the sidewall on top, but much more shallow than body layer 160.In splitting bar device, the ion implantation degree of depth of body layer 160 will meet some requirements: the position of body layer 160 and the interface of epitaxial loayer 110 near active groove 112, termination groove 111, outline is higher than the position of electric conducting material 150a, 150b bottom surface, so that raceway groove set up by the inversion layer that can be formed in vertical direction along the sidewall of active groove 112 or termination groove 111 in body layer 160.
In Fig. 1 O, deposit an insulating passivation layer 190 (as low temperature oxide LTO and/or the silex glass BPSG containing boric acid), cover on Semiconductor substrate upper surface, it has also merged original insulating barrier 118 on Semiconductor substrate upper surface.Insulating passivation layer 190 also covers the top of insulating material 145b, electric conducting material 150b and 150a simultaneously.After preparing insulating passivation layer 190, to need above insulating passivation layer 190 extra spin coating photoresist layer again, and some patterns of openings formed wherein, utilize this photoresist layer as contact hole etching mask, after suitable anisotropic dry etch, form some contact holes 303 running through insulating passivation layer 190 thickness.
Contact hole 303 extends downwardly in the body layer 160 of active area 320, also runs through the top doped layer 170 of active area 320.In certain embodiments, some contact holes 303 extend downwardly in the body layer 160 between adjacent two active grooves 112, and some contact holes 303 extend downwardly in the body layer 160 in the multiple active grooves 112 be arranged side by side between an outermost active groove 112 and termination groove 111.In some embodiment, termination groove 111 can be closed ring-shaped groove, and this active groove 112 outermost is exactly an active groove near the part being parallel to active groove 112 of termination groove 111 in fact.Notice that the step injecting heavily doped body contact region (P+ type) in the body layer 160 of contact hole 303 bottom periphery does not illustrate in the drawings.
In Fig. 1 O, at the bottom of each contact hole 303 and sidewall and a barrier metal layer can be deposited on the upper surface of insulating passivation layer 190, and then fill metal material (as tungsten) in each contact hole 303, the barrier metal layer in contact hole 303 and metal material form metal plug or metal joint jointly.
Then, then prepare the top that a metal layer at top covers whole insulating passivation layer 190, if insulating passivation layer 190 upper surface deposits barrier metal layer in advance, then metal layer at top essence covers on barrier metal layer.Afterwards patterning is implemented to them, segmentation metal layer at top and barrier metal layer, at least prepare a top metal electrode 220.Top metal electrode 220 (as source electrode) at least overlaps on part active area 320.They by the body layer 160 of active area 320, top doped layer 170 short circuit, and are electrically connected to top metal electrode 220 by the metal plug in contact hole 303.In an alternate embodiment of the invention, in the dimension do not illustrated, the active groove 112 of strip can be communicated with the part perpendicular to active groove 112 of termination groove 111, so that the electric conducting material 140b of the electric conducting material 140a of active groove 112 bottom and termination groove 111 bottom interconnects, electric conducting material 140a, 140b are electrically connected to top metal electrode 220, are in source potential.In addition, in the dimension do not illustrated, the electric conducting material 150b that the electric conducting material 150a on active groove 112 top and termination groove 111 top are filled interconnects, be connected on the electric conducting material in the grid pickup groove that do not illustrate, and electric conducting material 150a, 150b can to export to above insulating passivation layer 190 on a gate metal electrode by the metal plug aiming at and contact the electric conducting material that grid picks up in groove simultaneously.In addition, one is covered in the bottom metal electrode do not illustrated on base substrate 100 bottom surface as drain electrode.
FET unit or transistor unit cell are integrated in active area 320, the electric conducting material 140a of active groove 112 bottom is as the dhield grid of MOS transistor unit, the electric conducting material 150a on top is as the control gate of MOS transistor unit, control gate 150a overlaps on dhield grid 140a, relies on the dielectric isolation layer 145c between them both to be electrically insulated from each other.In active groove 112 or termination groove 111, the insulating barrier 118 (or being referred to as the second insulating barrier) as grid oxic horizon is thinner than the insulating barrier 116 (or being referred to as the first insulating barrier) that the sidewall of groove 111,112 bottom or bottom adhere to.
More special is, a part for the original insulating material 145 in termination groove 111 top is etched away, the electric conducting material 150b then filled is also as a gate electrode, can along this termination groove 111 top near the sidewall of active area 320 or center wafer side, vertical channel region is built in body layer 160, and using the insulating barrier 118 on the sidewall being attached to this side as grid oxic horizon.In addition, the insulating barrier 145b of termination groove 111 top on the sidewall of side, termination area 310 (or being referred to as the 3rd insulating barrier) is than insulating barrier 116,118 much thick, and this insulating barrier 145b is exactly that insulating material 145 is filled in termination groove 111 top and is not etched and that part of retaining in fact.The bucking electrode 140b of gate electrode 150b and below is electrically insulated from each other by the dielectric isolation layer 145c between them.
The symmetrical center line AA of gate electrode 150b on its Width, do not overlap with termination groove 111 symmetrical center line BB in the direction of the width, this center line AA to the distance of termination groove 111 near side, termination environment 310 sidewall, than large near the distance of side, active area 320 sidewall to termination groove 111.In view of the symmetrical center line AA of gate electrode 150b offset by some distances to active area 320 or center wafer, can think that gate electrode 150b is arrange in a non-symmetrical way on termination groove 111 top, offset by a little slightly towards active area 320 or center wafer.
The structure of Fig. 2 and Fig. 1 M is substantially identical, and except difference between the degree of depth of active groove 112 and the degree of depth of termination groove 111 is comparatively large, this is usually Problems existing (i.e. the result of Figure 1B) in the prior art.The difference that the depth value presetting darker termination groove 111 deducts the depth value of active groove 112 is T, when carrying out puncture voltage emulation between the source electrode and drain electrode of TrenchedMOSFET device, T value embodies device different withstand voltage properties time different: T value is larger, the breakdown voltage resistant ability of device is less, vice versa, T value is less, and the breakdown voltage resistant ability of device is larger.
When T value is larger, the puncture voltage of device is subject to termination environment clamping down on compared with low breakdown voltage.Such as, during MOSFET element operates in non-clamped Inductive switch UIS (Un-dampedInductiveSwitching) handover event, the bottom corners position of termination groove 111 is avalanche breakdown weakness, be easy to bring out avalanche breakdown at the bottom corners place of termination groove 111, especially the bottom corners of the side, close active area 320 of termination groove 111, to ionization by collision be there is in avalanche breakdown process, produce avalanche current.Avalanche breakdown is generally easy causes hot carrier's effect, when when puncturing close to insulating barrier 116 (as an oxide layer) vicinity, adverse consequences is that hot carrier can be captured and is injected in insulating barrier 116, thus damage or fracture grid oxic horizon, bring out the integrity problem that power device is long-term.According to the present invention's spirit, reduce T value, in termination environment 310 near the electric field strength at the bottom corners place of the termination groove 111 of active area 320 and crowding retarded, effectively inhibit the probability of termination environment 310 breakdown weak points generation avalanche breakdown, improve the puncture voltage of termination environment and the robustness of device, such as, embody puncture voltage (BVDSS) between the drain-source of MOSFET element when gate-source short circuit and be greatly improved.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (14)
1. a preparation method for groove power semiconductor device, is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, comprises base substrate and be positioned at the epitaxial loayer above base substrate;
Etching epitaxial loayer, is formed with the active groove of tool first degree of depth in source region, and the termination groove of the tool desired depth of formation termination environment, and the desired depth value of the first depth ratio termination groove is little;
Utilize a mask to cover on termination groove but expose active groove;
The step continuing to implement to etch, to increase the degree of depth of active groove, obtains the active groove of tool second degree of depth of expection;
Difference between the desired depth of wherein second degree of depth and termination groove is less than the difference between first degree of depth and the desired depth of termination groove.
2. the method for claim 1, is characterized in that, in the step of etching epitaxial loayer, first arranges a hard mask layer and to cover on Semiconductor substrate and to form opening wherein;
For etching the size of the opening preparing active groove, less than the size of the opening for etching preparation termination groove, make termination groove wider than active groove, and nationality is faster than the etch rate forming active groove by the etch rate forming termination groove, makes the desired depth of termination groove darker than first degree of depth.
3. the method for claim 1, is characterized in that, also comprises: at the respective bottom of active groove, termination groove and sidewall insulation liner layer, and filled conductive material is in active groove, termination groove;
Return and carve electric conducting material, only retain the electric conducting material of active groove, termination groove bottom separately;
Fill insulant is to active groove, termination groove top separately;
Return the insulating material carved in active groove, and return a part of insulating material carved near side, active area in the termination groove of termination environment, a dielectric isolation layer on the electric conducting material simultaneously retaining active groove, termination groove bottom separately;
Active groove, the termination groove sidewall that top is exposed separately covers another insulating barrier, and again filled conductive material to active groove, termination groove top separately.
4. method as claimed in claim 3, it is characterized in that, also comprise: implant the top of the ion contrary with Semiconductor substrate conduction type to epitaxial loayer, form the lateral wall circumference that a body layer is at least centered around active groove top, implant the ion identical with Semiconductor substrate conduction type subsequently to the top of body layer, form a top doped layer.
5. method as claimed in claim 3, it is characterized in that, after fill insulant to active groove, termination groove top separately, the part of insulating material near termination environment that the top of termination groove is filled is blocked by a mask, but the another part near active area is exposed from this mask, thus the electric conducting material making termination groove top fill offsets to active area.
6. the method for claim 1, is characterized in that, second degree of depth difference between the two that the desired depth of reduction termination groove and active groove finally have, and makes their difference close to 0, with the avalanche breakdown suppressing termination trench bottom corner place to bring out.
7. a groove power semiconductor device, is characterized in that, comprising:
A Semiconductor substrate including base substrate and be positioned at the epitaxial loayer above base substrate;
Second groove of the first groove being arranged in the epitaxial loayer of termination environment and the epitaxial loayer being arranged in active area;
The width of the second groove and the degree of depth of second groove narrower than the first groove is not less than the degree of depth of the first groove.
8. groove power semiconductor device as claimed in claim 7, is characterized in that, when there is avalanche breakdown, avalanche breakdown occurs in active area.
9. groove power semiconductor device as claimed in claim 7, it is characterized in that, the first groove and the second groove have the identical degree of depth.
10. groove power semiconductor device as claimed in claim 7, is characterized in that, the first trenched side-wall is attached with the oxide layer that one deck is thicker than the grid oxic horizon that the second trenched side-wall is arranged.
11. groove power semiconductor devices as claimed in claim 7, is characterized in that, extend in the epitaxial loayer of a body zone contrary with epitaxial loayer conduction type between the first groove and the second groove.
12. groove power semiconductor devices as claimed in claim 11, is characterized in that, a source area contrary with body zone conduction type extends between the first groove and the second groove, is positioned at body zone top.
13. groove power semiconductor devices as claimed in claim 12, it is characterized in that, body zone and source area are centered around the first groove both sides.
14. groove power semiconductor devices as claimed in claim 12, it is characterized in that, body zone and source area are centered around the second groove both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410478892.6A CN105489649B (en) | 2014-09-18 | 2014-09-18 | Improve the method for termination environment low breakdown voltage in groove-type power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410478892.6A CN105489649B (en) | 2014-09-18 | 2014-09-18 | Improve the method for termination environment low breakdown voltage in groove-type power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105489649A true CN105489649A (en) | 2016-04-13 |
| CN105489649B CN105489649B (en) | 2018-06-15 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107104149A (en) * | 2017-05-25 | 2017-08-29 | 中山汉臣电子科技有限公司 | A kind of power semiconductor |
| CN107910271A (en) * | 2017-11-17 | 2018-04-13 | 杭州士兰集成电路有限公司 | Power semiconductor and its manufacture method |
| CN111755526A (en) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | Trench MOS device and preparation method |
| CN111863705A (en) * | 2020-07-23 | 2020-10-30 | 中国科学院微电子研究所 | Method for forming isolation of semiconductor device |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
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| US20050181577A1 (en) * | 2003-12-19 | 2005-08-18 | Third Dimension (3D) Semiconductor, Inc. | Method of manufacturing a superjunction device |
| CN101371343A (en) * | 2006-01-25 | 2009-02-18 | 飞兆半导体公司 | Self-aligned trench MOSFET structure and method of manufacture |
| CN102246306A (en) * | 2008-12-08 | 2011-11-16 | 飞兆半导体公司 | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
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| US20050181577A1 (en) * | 2003-12-19 | 2005-08-18 | Third Dimension (3D) Semiconductor, Inc. | Method of manufacturing a superjunction device |
| CN101371343A (en) * | 2006-01-25 | 2009-02-18 | 飞兆半导体公司 | Self-aligned trench MOSFET structure and method of manufacture |
| CN102246306A (en) * | 2008-12-08 | 2011-11-16 | 飞兆半导体公司 | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104149A (en) * | 2017-05-25 | 2017-08-29 | 中山汉臣电子科技有限公司 | A kind of power semiconductor |
| CN107104149B (en) * | 2017-05-25 | 2020-04-07 | 中山汉臣电子科技有限公司 | Power semiconductor device |
| CN107910271A (en) * | 2017-11-17 | 2018-04-13 | 杭州士兰集成电路有限公司 | Power semiconductor and its manufacture method |
| CN107910271B (en) * | 2017-11-17 | 2023-11-17 | 杭州士兰集成电路有限公司 | Power semiconductor device and method of manufacturing the same |
| CN111863705A (en) * | 2020-07-23 | 2020-10-30 | 中国科学院微电子研究所 | Method for forming isolation of semiconductor device |
| CN111863705B (en) * | 2020-07-23 | 2024-04-23 | 中国科学院微电子研究所 | Method for forming isolation of semiconductor device |
| CN111755526A (en) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | Trench MOS device and preparation method |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
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