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CN105448914B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN105448914B
CN105448914B CN201410432231.XA CN201410432231A CN105448914B CN 105448914 B CN105448914 B CN 105448914B CN 201410432231 A CN201410432231 A CN 201410432231A CN 105448914 B CN105448914 B CN 105448914B
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China
Prior art keywords
laying
groove
substrate
area
forming method
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CN201410432231.XA
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CN105448914A (zh
Inventor
徐宽
陈武佳
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201410432231.XA priority Critical patent/CN105448914B/zh
Priority to US14/819,508 priority patent/US9559017B2/en
Publication of CN105448914A publication Critical patent/CN105448914A/zh
Priority to US15/384,109 priority patent/US20170140998A1/en
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Publication of CN105448914B publication Critical patent/CN105448914B/zh
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Abstract

一种半导体结构及其形成方法，所述形成方法包括：提供衬底，所述衬底具有第一区域和第二区域；在所述衬底的第一区域内形成第一沟槽；在所述衬底的第二区域内形成第二沟槽；在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层；对所述第一衬垫层进行氮化处理，在所述第一衬垫层内掺杂氮离子；在所述氮化处理工艺之后，去除第一区域的第一衬垫层；在去除第一区域的第一衬垫层之后，在所述第一沟槽的侧壁和底部表面形成第二衬垫层。所形成的半导体结构性能改善。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
浅沟槽隔离结构(Shallow Trench Isolation，简称STI)在目前的半导体器件制造中常用于隔离有源区。图1至图3是现有技术的浅沟槽隔离结构的形成过程的剖面结构示意图。
请参考图1，提供衬底100，所述衬底100内具有沟槽101。
请参考图2，在所述衬底100表面和沟槽101(如图1所示)内形成填充满所述沟槽101的隔离膜102。
请参考图3，对所述隔离膜102进行抛光，制造暴露出所述衬底100表面为止，在所述沟槽101(如图1所示)内形成浅沟槽隔离结构103。
随着半导体技术的发展，半导体器件的特征尺寸不断缩小，而集成度不断提高，导致所述浅沟槽隔离结构的尺寸也相应减小，相应的，用于形成浅沟槽隔离结构的沟槽深宽比(aspect ratio)不断增大，容易导致在沟槽101内形成的隔离膜102内部具有空隙，影响所形成的浅沟槽隔离结构103的隔离性能。因此，为了提高所形成的隔离膜102的质量，所述隔离膜102能够采用高深宽比填孔工艺(HARP，High Aspect Ratio Process)形成，以满足更高深宽比沟槽的填充需求，使形成于沟槽101内的隔离膜102内部的无空隙。
然而，采用高深宽比工艺形成的浅沟槽隔离结构会后续形成于衬底内或衬底表面的半导体器件产生不良影响，导致所形成的半导体器件的性能降低。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，所形成的半导体结构性能改善。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底具有第一区域和第二区域；在所述衬底的第一区域内形成第一沟槽；在所述衬底的第二区域内形成第二沟槽；在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层；对所述第一衬垫层进行氮化处理，在所述第一衬垫层内掺杂氮离子；在所述氮化处理工艺之后，去除第一区域的第一衬垫层；在去除第一区域的第一衬垫层之后，在所述第一沟槽的侧壁和底部表面形成第二衬垫层。
可选的，在所述氮化处理工艺之前，所述第一衬垫层的材料为氧化硅。
可选的，所述第一衬垫层的形成工艺为原位蒸汽生成工艺。
可选的，所述第二衬垫层的材料为氧化硅。
可选的，所述第二衬垫层的形成工艺为快速热氧化工艺或原位蒸汽生成工艺。
可选的，所述氮化处理工艺包括快速热氮化工艺。
可选的，所述快速热氮化工艺包括：气体包括含氮气体，气体流量为8slm～12slm，压力为600torr～700torr，温度为750℃～850℃。
可选的，所述含氮气体包括氨气。
可选的，在所述快速热氮化工艺之后，还包括对所述第一衬垫层进行快速热氧化处理。
可选的，所述快速热氧化处理的气体包括N2O、O2、H2O中的一种或多种，温度为1000℃～1200℃。
可选的，去除第一区域的第一衬垫层的工艺为湿法刻蚀工艺。
可选的，所述湿法刻蚀工艺的刻蚀液包括氢氟酸、硫酸、双氧水和水。
可选的，所述第一沟槽和第二沟槽的形成工艺包括：在衬底表面形成掩膜层，所述掩膜层暴露出部分第一区域和第二区域的衬底表面；以所述掩膜层为掩膜，刻蚀所述衬底，在所述衬底的第一区域内形成第一沟槽，在所述衬底的第二区域内形成第二沟槽。
可选的，在刻蚀所述衬底之后，去除所述第一沟槽和第二沟槽周围的部分掩膜层，并暴露出第一沟槽和第二沟槽周围的部分衬底表面。
可选的，所述掩膜层包括氮化硅层。
可选的，所述掩膜层还包括位于所述氮化硅层和衬底之间的氧化硅层。
可选的，还包括：在形成所述第一衬垫层和第二衬垫层之后，在所述第一衬垫层和第二衬垫层表面形成填充满第一沟槽和第二沟槽的隔离结构。
可选的，所述隔离结构的材料包括氧化硅。
可选的，在衬底的第一区域形成NMOS晶体管；在衬底的第二区域形成PMOS晶体管。
相应的，本发明还提供一种采用上述任一项方法所形成的半导体结构，包括：衬底，所述衬底具有第一区域和第二区域；位于所述衬底第一区域内的第一沟槽；位于所述衬底第二区域内的第二沟槽；位于所述第二沟槽的侧壁和底部表面的第一衬垫层，所述第一衬垫层内掺杂有氮离子；位于所述第一沟槽的侧壁和底部表面的第二衬垫层。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的形成方法中，所述衬底具有分别用于形成不同导电类型器件的第一区域和第二区域，并且分别在第一区域的衬底内形成第一沟槽，在第二区域的衬底内形成第二沟槽。在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层之后，在所述第一衬垫层内掺杂氮离子，使所述第一衬垫层与衬底之间的应力能够被释放，避免所述第一衬垫层降低后续形成于第二区域的器件性能。而且，所掺杂的氮离子还能够提高所述第一衬垫层的阻挡作用，避免衬底内掺杂的离子向后续形成于第二沟槽内的隔离结构扩散。之后，去除第一区域的第一衬垫层，并在第一沟槽的侧壁和底部表面形成第二衬垫层，所述第二衬垫层能够对衬底施加应力，所述应力能够提高后续形成于第一区域的器件性能。同时，所述第二衬垫层还能够阻挡衬底内的掺杂离子向后续形成于第一沟槽内的隔离结构扩散。因此，形成于第一区域的器件性能得到提高，同时，形成于第二区域的器件性能也得到提高。
进一步，在所述氮化处理工艺之前，所述第一衬垫层的材料为氧化硅，所述第一衬垫层的形成工艺为原位蒸汽生成(In-Situ Steam Generation，简称ISSG)工艺。所述原位蒸汽生成工艺所形成的氧化硅层覆盖能力好，适用于在高深宽比的第一沟槽和第二沟槽内形成第一衬垫层，而且能够使所形成的第一衬垫层厚度均匀，有利于保证所述第一衬垫层的隔离效果。
进一步，所述第二衬垫层的材料为氧化硅，所述第二衬垫层的形成工艺为快速热氧化工艺或原位蒸汽生成工艺。采用所述快速热氧化工艺或原位蒸汽生成工艺形成的氧化硅层与衬底之间会产生晶格失配，从而使所述第二衬垫层能够与衬底之间产生拉应力，所述拉应力能够提高用于形成于第一区域的器件性能。同时，在所述原位蒸汽生成工艺形成第二衬垫层的过程中，能够使第一区域内，处于第一衬垫层和衬底界面处的氮离子向所述第一衬垫层内扩散，进一步提高第一衬垫层隔离衬底内掺杂离子的效果。
进一步，对所述第一衬垫层进行氮化处理的工艺包括快速热氮化工艺，且在所述快速热氮化工艺之后，还包括对所述第一衬垫层进行快速热氧化处理。所述快速热氧化处理能够使所述第一衬垫层更为致密均匀，以此提高所述第一衬垫层的隔离效果。
进一步，所述衬底表面具有掩膜层，所述掩膜层用于作为掩膜刻蚀形成第一沟槽和第二沟槽，在刻蚀所述衬底之后，去除所述第一沟槽和第二沟槽周围的部分掩膜层，并暴露出第一沟槽和第二沟槽周围的部分衬底表面。后续形成的第一衬垫层和第二衬垫层还能够位于所暴露出的衬底表面，并且使第一沟槽和第二沟槽的侧壁和衬底表面所构成的顶角成为圆角，有利于后续在所述第一沟槽和第二沟槽内填充隔离结构的材料，避免因第一沟槽或第二沟槽顶部过早闭合，而在所形成的隔离结构内产生空穴的问题。
本发明的结构中，所述衬底具有第一区域和第二区域，所述第一区域和第二区域的器件导电类型不同，所述第一区域的衬底内具有第一沟槽，所述第二区域的衬底内具有第二沟槽。所述第二沟槽的侧壁和底部表面具有第一衬垫层，所述第一衬垫层内掺杂有氮离子，使所述第一衬垫层与衬底之间的应力能够被释放，避免所述第一衬垫层降低第二区域的器件性能。而且，所掺杂的氮离子还能够提高所述第一衬垫层的阻挡作用，避免衬底内掺杂的离子向第二沟槽内的隔离结构扩散。所述第一沟槽的侧壁和底部表面具有第二衬垫层，所述第二衬垫层能够对衬底施加应力，所述应力能够提高第一区域的器件性能。同时，所述第二衬垫层还能够阻挡衬底内的掺杂离子向第一沟槽内的隔离结构扩散。因此，形成于第一区域的器件性能得到提高，同时，形成于第二区域的器件性能也得到提高。
附图说明
图1至图3是现有技术的浅沟槽隔离结构的形成过程的剖面结构示意图；
图4是在衬底内形成浅沟槽隔离结构和有源区，并在衬底表面形成栅极结构之后的俯视结构示意图；
图5至图13是本发明实施例的半导体结构的形成过程的剖面结构示意图。
具体实施方式
如背景技术所述，采用高深宽比工艺形成的浅沟槽隔离结构会导致后续形成的半导体器件的性能降低。
经过研究发现，请继续参考图3，由于所述浅沟槽隔离结构103的材料为氧化硅，而衬底100的材料为单晶硅，采用所述高深宽比工艺所形成的隔离膜102与衬底200的界面处会产生晶格失配；而且，所形成的氧化硅晶格常数小于单晶硅的晶格常数，导致所形成的浅沟槽隔离结构103会对所述衬底100产生拉应力。所述拉应力虽然能够提高NMOS晶体管沟道区的载流子迁移率，但对于PMOS晶体管来说，所述拉应力会导致沟道区的载流子迁移率下降。
具体请参考图4，图4是在衬底内形成浅沟槽隔离结构和有源区，并在衬底表面形成栅极结构之后的俯视结构示意图，包括：衬底200；位于衬底200内的有源区201，所述有源区201呈矩阵阵列排列；位于相邻有源区201之间的浅沟槽隔离结构202，所述浅沟槽隔离结构202沿相互垂直的X方向和Y方向将有源区201相互隔离；位于所述有源区201表面的栅极结构203，所述栅极结构203平行于Y方向，而载流子沿所述X方向在所述栅极结构203底部的沟道区内移动。
其中，与所述Y方向平行的浅沟槽隔离结构202会对有源区201施加沿X方向的拉应力，所述拉应力与载流子的移动方向一致。当所述栅极结构203用于形成NMOS晶体管时，所述拉应力会提高沟道区的载流子迁移率，从而提高NMOS晶体管的性能。然而，当所述栅极结构203用于形成PMOS晶体管时，所述拉应力会导致沟道区的载流子迁移率下降，致使PMOS晶体管的性能下降。
在一实施例中，为了释放所述浅沟槽隔离结构对衬底施加的拉应力，在所述浅隔离结构和衬底之间形成了掺氮的氧化硅衬垫层。所述掺氮的氧化硅衬垫层处于浅沟槽隔离结构和衬底之间的界面处，能够释放所述浅沟槽隔离结构与衬底之间的晶格失配，从而释放所述浅沟槽隔离结构对衬底施加的拉应力。
然而，虽然在浅隔离结构和衬底之间形成了掺氮的氧化硅衬垫层能够释放所述浅沟槽隔离结构对衬底施加的拉应力，有利于提高PMOS晶体管的性能，但是，对于NMOS晶体管来说，失去了所述浅沟槽隔离结构对衬底施加的拉应力，会导致NMOS晶体管沟道区的载流子迁移率下降。
为了解决上述问题，本发明提出一种半导体结构及其形成方法。其中，衬底具有分别用于形成NMOS晶体管的第一区域和用于形成PMOS晶体管的第二区域；分别在第一区域的衬底内形成第一沟槽，在第二区域的衬底内形成第二沟槽；在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层之后，在所述第一衬垫层内掺杂氮离子，所述第一衬垫层内掺杂氮离子能够释放所述第一衬垫层与衬底之间的应力，使得所述第一衬垫层不降低需要形成于第二区域的器件性能；而且，所掺杂的氮离子还能够提高所述第一衬垫层的阻挡作用，避免衬底内掺杂的离子向后续形成于第二沟槽内的隔离结构扩散。之后，去除第一区域的第一衬垫层，并在第一沟槽的侧壁和底部表面形成第二衬垫层，所述第二衬垫层能够对衬底施加应力，同时，所述第二衬垫层还能够阻挡衬底内的掺杂离子向后续形成于第一沟槽内的隔离结构扩散。因此，形成于第一区域的器件性能得到提高，同时，形成于第二区域的器件性能也得到提高。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图13是本发明实施例的半导体结构的形成过程的剖面结构示意图。
请参考图5，提供衬底300，所述衬底300具有第一区域301和第二区域302。
所述衬底300为硅衬底、硅锗衬底、碳化硅衬底、绝缘体上硅衬底、绝缘体上锗衬底、玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)。本实施例中，所述衬底300为硅衬底。
本实施例中，所述第一区域301用于形成NMOS晶体管，因此，在所述衬底300的第一区域301内形成P型阱区；所述第二区域302用于形成PMOS晶体管，因此，在所述衬底300的第二区域302内形成N型阱区；所述P型阱区和N型阱区采用离子注入工艺形成。
后续需要在所述衬底300的第一区域301内形成第一沟槽，在所述衬底300的第二区域302内形成第二沟槽，以下将对所述第一沟槽和第二沟槽的形成工艺进行说明。
请参考图6，在衬底300表面形成掩膜层310，所述掩膜层310暴露出部分第一区域301和第二区域302的衬底300表面。
所述掩膜层310用于作为后续在衬底300内形成第一沟槽和第二沟槽的掩膜。本实施例中，所述掩膜层310包括氮化硅层311，且所述掩膜层310还包括位于所述氮化硅层311和衬底300之间的氧化硅层312；其中，所述氮化硅层311的硬度较高，能够在后续的刻蚀过程中保持图形的稳定性，所述氧化硅层312用于提高所述氮化硅层311和衬底300之间的结合强度，避免在后续的刻蚀过程中，发生氮化硅层311剥离的现象。在其它实施例中，所述掩膜层310还能够仅为氮化硅层。
所述掩膜层310的形成工艺包括：在衬底300的表面形成氧化硅膜；在所述氧化硅膜表面形成氮化硅膜；在所述氮化硅膜表面形成图形化的光刻胶层，所述图形化层的光刻胶层暴露出需要第一沟槽和第二沟槽的对应区域；以所述图形化的光刻胶层为掩膜，刻蚀所述氮化硅膜和氧化硅膜，直至暴露出衬底300表面为止，形成氮化硅层311和氧化硅层312。本实施例中，在刻蚀所述氮化硅膜和氧化硅膜之后，去除所述图形化的光刻胶层。在其它实施例中，还能够在刻蚀所述氮化硅膜和氧化硅膜之后，保留所述图形化的光刻胶层。
请参考图7，以所述掩膜层310为掩膜，刻蚀所述衬底300，在所述衬底300的第一区域301内形成第一沟槽321，在所述衬底300的第二区域302内形成第二沟槽322。
所述第一沟槽321用于在第一区域301形成浅沟槽隔离结构，所述第二沟槽322用于在第二区域302形成浅沟槽隔离结构。所述形成第一沟槽321和第二沟槽322的刻蚀工艺为各向异性的干法刻蚀工艺，能够使所形成的第一沟槽321和第二沟槽322的侧壁相对于衬底300表面垂直，或者能够使所形成的第一沟槽321和第二沟槽322的侧壁相对于衬底300表面倾斜，且所述第一沟槽321和第二沟槽322的顶部尺寸大于底部尺寸。
在本实施例中，第一沟槽321和第二沟槽322的侧壁相对于衬底300表面倾斜，且所述第一沟槽321和第二沟槽322的顶部尺寸大于底部尺寸，所述侧壁相对于衬底300表面的倾斜角度能够通过调整刻蚀工艺的参数进行调节。当所述侧壁相对于衬底300表面倾斜时，后续易于在所述第一沟槽321和第二沟槽322内填充材料，有利于使后续形成的衬垫层厚度均匀，且位于衬垫层表面的隔离结构内部均匀致密，不易在所述隔离结构内形成空洞。
本实施例中，所述第一沟槽321和第二沟槽322的深宽比大于5:1，所述第一沟槽321和第二沟槽322的深宽比较大，后续需要采用高深宽比沉积工艺在所述第一沟槽321和第二沟槽322内形成隔离结构。
所述形成第一沟槽321和第二沟槽322的各向异性的干法刻蚀工艺的参数包括：气体包括刻蚀气体，所述刻蚀气体为Cl2、HBr、或Cl2和HBr的混合气体，HBr的流量为200sccm～800sccm，Cl2的流量为20sccm～100sccm，此外，所述气体还包括惰性气体，例如Ar，所述惰性气体的流量为50sccm～1000sccm，刻蚀腔室的压力为2毫托～200毫托，刻蚀时间为15秒～60秒。
在本实施例中，所述掩膜层310在后续形成隔离结构之后去除，则位于衬底300表面的掩膜层310能够在后续形成隔离结构的工艺中，用于保护衬底300表面。
请参考图8，在刻蚀所述衬底300之后，去除所述第一沟槽321和第二沟槽322周围的部分掩膜层310，并暴露出第一沟槽321和第二沟槽322周围的部分衬底300表面。
在本实施例中，在刻蚀形成所述第一沟槽321和第二沟槽322之后，还需要采用回退工艺暴露出所述第一沟槽321和第二沟槽322周围的部分衬底300表面。由于在后续形成第一衬垫层或第二衬垫层的工艺中，需要以工艺气体与所暴露出的衬底300表面、以及第一沟槽321或第二沟槽322的侧壁或底部表面进行反应，用于形成所述第一衬垫层或第二衬垫层，从而在所述第一沟槽321或第二沟槽322的侧壁与衬底300所构成的顶角处，由于工艺气体能够同时对暴露出的衬底300表面、以及第一沟槽321或第二沟槽322的侧壁表面进行氧化，使得所述顶角处的氧化速率较快，而且工艺的温度较高，从而能够使所述顶角处形成的衬垫层表面成为圆角，进而有利于后续在所述第一沟槽321或第二沟槽322内填充隔离结构的材料，避免因第一沟槽321或第二沟槽322的顶部过早闭合，而在隔离结构内产生空穴。
所述回退工艺为各向同性的刻蚀工艺，而且所述各向同性的刻蚀工艺能够为干法刻蚀工艺或湿法刻蚀工艺。所述各向同性的刻蚀工艺在各个方向上均具有较高的刻蚀速率，从而能够以平行于衬底300表面的方向对所述掩膜层310进行刻蚀，以扩大所述掩膜层310暴露出的区域面积，从而暴露出第一沟槽321和第二沟槽322周围的部分衬底300表面。
在本实施例中，所述各向同性的刻蚀工艺为湿法刻蚀工艺，且由于所述掩膜层310包括氧化硅层312和氮化硅层311，因此所述湿法刻蚀工艺的刻蚀液包括氢氟酸溶液和磷酸溶液，并通过调节所述氢氟酸和磷酸的比例，调节所述刻蚀工艺对氧化硅层312和氮化硅层311的刻蚀速率。在其它实施例中，所述各向同性的刻蚀工艺为干法刻蚀工艺，所述干法刻蚀的气体包括CF4、CHF3，电压小于10伏，功率小于100瓦，气压小于1毫托。
请参考图9，在所述第一沟槽321和第二沟槽322的侧壁和底部表面形成第一衬垫层331。
所述第一衬垫层331用于提高衬底300和后续形成的隔离结构之间的隔离效果，避免因衬底300内所掺杂的离子向所述隔离结构内扩散而降低隔离结构的隔离能力。
在本实施例中，所述第一衬垫层331的材料为氧化硅，厚度为10埃～200埃，所述第一衬垫层331的形成工艺为原位蒸汽生成工艺，所述原位蒸汽生成工艺的参数包括：温度为700℃～1200℃，气体包括氢气和氧气，氧气流量为1sccm～30sccm，氢气流量为1.5sccm～15sccm，时间为1分钟～10分钟。
所述原位蒸汽生成工艺需要以工艺气体与暴露出的衬底300表面、以及第一沟槽321和第二沟槽322的侧壁和底部表面进行反应，以形成所述第一衬垫层331。所述原位蒸汽生成工艺所形成的氧化硅材料层覆盖能力好，能够使所形成的第一衬垫层331与第一沟槽321和第二沟槽322的侧壁和底部表面紧密贴合，而且所述第一衬垫层331的厚度均匀、密度较大，因此所述第一衬垫层331具有良好的隔离效果。
在本实施例中，在所述第一沟槽321和第二沟槽322的侧壁与衬底300表面构成的顶角处，由于工艺气体能够同时与衬底300表面、以及第一沟槽321和第二沟槽322的侧壁表面进行反应，使得所述顶角处的氧化速率较高，而且，由于所述原位蒸汽生成工艺的温度较高，从而能够形成于所述顶角表面第一衬垫层331表面成为圆角，使得第一沟槽321和第二沟槽322的顶部尺寸扩大，有利于后续在所述第一沟槽321和第二沟槽322内形成隔离结构，避免所形成的隔离结构内形成空洞，使所述隔离结构的隔离效果较好。
然而，由于所形成的第一衬垫层331与衬底300之间存在晶格失配，使得所述第一衬垫层331会对衬底300提供应力，而本实施例中，所述第一衬垫层331的材料为氧化硅，所述第一衬垫层331会对所述衬底300提供拉应力；在本实施例中，所述第一区域301用于形成NMOS晶体管，所述第二区域302用于形成PMOS晶体管，所述第一衬垫层331提供的拉应力会降低第二区域302形成的PMOS晶体管沟道区的载流子迁移率。因此，后续需要对所述第一衬垫层331进行氮化处理，以释放所述第一衬垫层331对衬底300施加的应力。
请参考图10，对所述第一衬垫层331进行氮化处理，在所述第一衬垫层331内掺杂氮离子。
所述氮化处理工艺包括快速热氮化工艺，所述快速热氮化工艺包括：气体包括含氮气体，气体流量为8slm～12slm，压力为600torr～700torr，温度为750℃～850℃。本实施例中，所述含氮气体为氨气，气体流量为10slm，压力为650torr，温度为800℃。经过所述快速热氮化工艺之后，所述第一衬垫层331的材料成为氮氧化硅。
在所述热氮化工艺中，所述含氮气体中的氮离子受到热驱动而向所述第一衬垫层331内扩散，所掺杂的氮离子能够打乱所述第一衬垫层331的晶格结构，使所述第一衬垫层331的晶格常数发生变化，使得第一衬垫层331与衬底300之间的化学键被打断，从而使所述第一衬垫层331与衬底300之间的拉应力被释放，从而避免所述第一衬垫层331降低后续形成于第二区域的PMOS晶体管的性能。
而且，在所述第一衬垫层331内掺杂的氮离子，还能够提高所述第一衬垫层331的硬度和密度，从而提高了所述第一衬垫层331的阻挡作用，进一步阻止衬底300内的掺杂离子向后续形成于第二沟槽322内的隔离结构扩散。
然而，由于所述氮化处理工艺释放了第一衬垫层331对所述衬底300施加的拉应力，使得所述第一沟槽321内的衬垫层331与衬底300之间的拉应力也被消除，而所述第一区域301用于形成NMOS晶体管，所述NMOS晶体管的沟道区需要拉应力以提高载流子迁移率，因此，所述氮化处理工艺会降低第一区域301所形成的NMOS晶体管的性能。因此，后续需要去除第一区域301的第一衬垫层331，并形成能够对衬底300施加拉应力的第二衬垫层。
在本实施例中，在所述快速热氮化工艺之后，还包括对所述第一衬垫层331进行快速热氧化处理。所述快速热氧化处理的气体包括N2O、O2、H2O中的一种或多种，温度为1000℃～1200℃，本实施例中的温度为1100℃。所述快速热氧化处理能够使所述第一衬垫层321更为致密均匀，以此提高所述第一衬垫层321的隔离效果。
请参考图11，在所述氮化处理工艺之后，去除第一区域301的第一衬垫层331。
所述去除第一区域301的第一衬垫层331的工艺包括：在第一衬垫层331表面形成图形化的光刻胶层400，所述光刻胶层400暴露出第一区域的第一衬垫层331表面；以所述光刻胶层400为掩膜，刻蚀所述第一衬垫层331，直至暴露出第一沟槽321的侧壁和底部表面为止。本实施例中，所述光刻胶层400的材料为KrF。
去除第一区域301的第一衬垫层331之后，能够在第一沟槽321的侧壁和底部表面形成第二衬垫层，使所述第二衬垫层对衬底300施加拉应力，从而提高形成于第一区域301的NMOS晶体管的性能。
在本实施例中，去除第一区域301的第一衬垫层331的工艺为湿法刻蚀工艺；所述湿法刻蚀工艺的刻蚀液包括氢氟酸和SPM清洗液；其中，氢氟酸用于去除氧化硅，SPM清洗液包括硫酸、双氧水和水，所述SPM清洗液用于去除氮化硅、以及残留于第一沟槽321侧壁和底部表面的刻蚀副产物。采用所述湿法刻蚀工艺去除所述第一衬垫层331，由于所述湿法刻蚀工艺的选择性较高，在去除所述第一衬垫层331时，对第一沟槽321的侧壁和底部表面的损伤较小，有利于保证后续形成的第二衬垫层的形貌良好，且第一沟槽321的尺寸精确。
请参考图12，在去除第一区域301的第一衬垫层331之后，在所述第一沟槽321的侧壁和底部表面形成第二衬垫层332。
本实施例中，在去除第一区域301的第一衬垫层331之后，去除所述光刻胶层400(如图11所示)。
所述第二衬垫层332用于提高衬底300和后续形成的隔离结构之间的隔离效果，阻挡衬底300内的掺杂离子向后续形成于第一沟槽321内的隔离结构扩散，避免所述隔离结构的隔离性能下降。
在本实施例中，所述第二衬垫层332的材料为氧化硅，厚度为10埃～200埃，所述第二衬垫层332的形成工艺为快速热氧化工艺或原位蒸汽生成工艺。在本实施例中，所述第二衬垫层332以原位蒸汽生成工艺形成，所述原位蒸汽生成工艺的参数包括：温度为700℃～1200℃，气体包括氢气和氧气，氧气流量为1sccm～30sccm，氢气流量为1.5sccm～15sccm，时间为1分钟～10分钟。
所述原位蒸汽生成工艺需要以工艺气体与暴露出的衬底300表面、以及第一沟槽321的侧壁和底部表面进行反应，以形成所述第二衬垫层332。所述原位蒸汽生成工艺所形成的氧化硅材料层覆盖能力好，能够使所形成的第二衬垫层332与第一沟槽321的侧壁和底部表面紧密贴合，而且所述第二衬垫层332的厚度均匀、密度较大，因此所述第二衬垫层332具有良好的隔离效果。
而且，所形成的第二衬垫层332与衬底300之间存在晶格失配，且所述第二衬垫层332的材料为氧化硅，从而使所述第二衬垫层332能够对衬底300施加拉应力，而所述第一区域301用于形成NMOS晶体管，则所述拉应力能够所述NMOS晶体管沟道区的载流子迁移率，从而提高所形成的NMOS晶体管的性能。
在本实施例中，在形成所述第二衬垫层332之后，去除覆盖第二区域302的光刻胶层。在其它实施例中，在形成所述第二衬垫层332之前，去除所述覆盖第二区域302的光刻胶层。
请参考图13，在形成所述第一衬垫层331和第二衬垫层332之后，在所述第一衬垫层331和第二衬垫层332表面形成填充满第一沟槽321(如图12所示)和第二沟槽322(如图12所示)的隔离结构340。
所述隔离结构340的材料包括氧化硅；所述隔离结构340的形成工艺包括：在掩膜层310表面、第一衬垫层331表面、以及第二衬垫层332表面形成隔离层；对所述隔离层进行平坦化工艺，直至暴露出衬底300表面为止，在第一沟槽321和第二沟槽322内形成隔离结构340。
本实施例中，所述平坦化工艺为化学机械抛光工艺，且在所述化学机械抛光工艺中，所述掩膜层310(如图12所示)作为抛光能够定义抛光工艺的停止位置，在所述抛光工艺暴露出所述掩膜层310表面之后，继续对所述掩膜层310进行抛光，直至暴露出衬底300表面为止。
本实施例中，所述第一沟槽321和第二沟槽322的深宽比较大，形成所述隔离层的工艺为高深宽比沉积工艺(HARP)，所述高深宽比的化学气相沉积工艺中，沉积气体包括正硅酸乙酯(Si(OC2H5)4)和臭氧(O3)，所述正硅酸乙酯的流量为500毫克/分钟～8000毫克/分钟，臭氧的流量为5000标准毫升/分钟～3000标准毫升/分钟，气压为300托～600托，温度为400摄氏度～600摄氏度；此外，沉积气体还包括：氮气、氧气和氦气，氮气的流量为1000标准毫升/分钟～10000标准毫升/分钟，氧气的流量为0标准毫升/分钟～5000标准毫升/分钟，氦气的流量为5000标准毫升/分钟～20000标准毫升/分钟。
本实施例中，所述衬底具有分别用于形成不同导电类型器件的第一区域和第二区域，并且分别在第一区域的衬底内形成第一沟槽，在第二区域的衬底内形成第二沟槽。在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层之后，在所述第一衬垫层内掺杂氮离子，使所述第一衬垫层与衬底之间的应力能够被释放，避免所述第一衬垫层降低后续形成于第二区域的器件性能。而且，所掺杂的氮离子还能够提高所述第一衬垫层的阻挡作用，避免衬底内掺杂的离子向后续形成于第二沟槽内的隔离结构扩散。之后，去除第一区域的第一衬垫层，并在第一沟槽的侧壁和底部表面形成第二衬垫层，所述第二衬垫层能够对衬底施加应力，所述应力能够提高后续形成于第一区域的器件性能。同时，所述第二衬垫层还能够阻挡衬底内的掺杂离子向后续形成于第一沟槽内的隔离结构扩散。因此，形成于第一区域的器件性能得到提高，同时，形成于第二区域的器件性能也得到提高。
相应的，本发明的实施例还提供一种采用上述方法所形成的半导体结构，请继续参考图13，包括：衬底300，所述衬底300具有第一区域301和第二区域302；位于所述衬底300第一区域301内的第一沟槽；位于所述衬底300第二区域302内的第二沟槽；位于所述第二沟槽的侧壁和底部表面的第一衬垫层331，所述第一衬垫层331内掺杂有氮离子；位于所述第一沟槽的侧壁和底部表面的第二衬垫层332。
本实施例中，所述衬底300的第一区域用于形成NMOS晶体管，所述衬底300的第二区域用于形成PMOS晶体管。所述第一衬垫层331的材料为氮氧化硅；所述第二衬垫层332的材料为氧化硅。
本实施例中，所述第一衬垫层331和第二衬垫层332表面还具有填充满所述第一沟槽和第二沟槽的隔离结构340。
本实施例中，所述衬底具有第一区域和第二区域，所述第一区域和第二区域的器件导电类型不同，所述第一区域的衬底内具有第一沟槽，所述第二区域的衬底内具有第二沟槽。所述第二沟槽的侧壁和底部表面具有第一衬垫层，所述第一衬垫层内掺杂有氮离子，使所述第一衬垫层与衬底之间的应力能够被释放，避免所述第一衬垫层降低第二区域的器件性能。而且，所掺杂的氮离子还能够提高所述第一衬垫层的阻挡作用，避免衬底内掺杂的离子向第二沟槽内的隔离结构扩散。所述第一沟槽的侧壁和底部表面具有第二衬垫层，所述第二衬垫层能够对衬底施加应力，所述应力能够提高第一区域的器件性能。同时，所述第二衬垫层还能够阻挡衬底内的掺杂离子向第一沟槽内的隔离结构扩散。因此，形成于第一区域的器件性能得到提高，同时，形成于第二区域的器件性能也得到提高。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底具有第一区域和第二区域；
在所述衬底的第一区域内形成第一沟槽；
在所述衬底的第二区域内形成第二沟槽；
在所述第一沟槽和第二沟槽的侧壁和底部表面形成第一衬垫层；
对所述第一衬垫层进行氮化处理，在所述第一衬垫层内掺杂氮离子；
在所述氮化处理工艺之后，去除第一区域的第一衬垫层；
在去除第一区域的第一衬垫层之后，在所述第一沟槽的侧壁和底部表面形成第二衬垫层，所述第二衬垫层的材料为氧化硅，所述第二衬垫层用于对衬底施加拉应力；
在衬底的第一区域形成NMOS晶体管；
在衬底的第二区域形成PMOS晶体管。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述氮化处理工艺之前，所述第一衬垫层的材料为氧化硅。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述第一衬垫层的形成工艺为原位蒸汽生成工艺。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二衬垫层的形成工艺为快速热氧化工艺或原位蒸汽生成工艺。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述氮化处理工艺包括快速热氮化工艺。
6.如权利要求5所述的半导体结构的形成方法，其特征在于，所述快速热氮化工艺包括：气体包括含氮气体，气体流量为8slm～12slm，压力为600torr～700torr，温度为750℃～850℃。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述含氮气体包括氨气。
8.如权利要求5所述的半导体结构的形成方法，其特征在于，在所述快速热氮化工艺之后，还包括对所述第一衬垫层进行快速热氧化处理。
9.如权利要求8所述的半导体结构的形成方法，其特征在于，所述快速热氧化处理的气体包括N2O、O2、H2O中的一种或多种，温度为1000℃～1200℃。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，去除第一区域的第一衬垫层的工艺为湿法刻蚀工艺。
11.如权利要求10所述的半导体结构的形成方法，其特征在于，所述湿法刻蚀工艺的刻蚀液包括氢氟酸、硫酸、双氧水和水。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一沟槽和第二沟槽的形成工艺包括：在衬底表面形成掩膜层，所述掩膜层暴露出部分第一区域和第二区域的衬底表面；以所述掩膜层为掩膜，刻蚀所述衬底，在所述衬底的第一区域内形成第一沟槽，在所述衬底的第二区域内形成第二沟槽。
13.如权利要求12所述的半导体结构的形成方法，其特征在于，在刻蚀所述衬底之后，去除所述第一沟槽和第二沟槽周围的部分掩膜层，并暴露出第一沟槽和第二沟槽周围的部分衬底表面。
14.如权利要求12所述的半导体结构的形成方法，其特征在于，所述掩膜层包括氮化硅层。
15.如权利要求12所述的半导体结构的形成方法，其特征在于，所述掩膜层还包括位于所述氮化硅层和衬底之间的氧化硅层。
16.如权利要求1所述的半导体结构的形成方法，其特征在于，还包括：在形成所述第一衬垫层和第二衬垫层之后，在所述第一衬垫层和第二衬垫层表面形成填充满第一沟槽和第二沟槽的隔离结构。
17.如权利要求16所述的半导体结构的形成方法，其特征在于，所述隔离结构的材料包括氧化硅。
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