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CN105304705A - Heterojunction high electron mobility spinning field effect transistor and manufacturing method - Google Patents

Heterojunction high electron mobility spinning field effect transistor and manufacturing method Download PDF

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CN105304705A
CN105304705A CN201510518723.5A CN201510518723A CN105304705A CN 105304705 A CN105304705 A CN 105304705A CN 201510518723 A CN201510518723 A CN 201510518723A CN 105304705 A CN105304705 A CN 105304705A
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source
drain
electrode
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CN105304705B (en
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贾仁需
彭博
吕红亮
张玉明
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Xinlian Power Technology Shaoxing Co ltd
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Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66431Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a heterojunction high electron mobility spinning field effect transistor and a manufacturing method. The transistor comprises a 3C-SiC drain region, a 3C-SiC source region, a 3C-SiC channel region, a Schottky contact gate electrode, an Si substrate, a drain electrode, a source electrode, and an SiN isolation layer. The 3C-SiC drain region, the 3C-SiC source region and the 3C-SiC channel region are located on the Si substrate. The source electrode is located in the 3C-SiC source region, the Schottky contact gate electrode is located in the 3C-SiC channel region, and the drain electrode is located in the 3C-SiC drain region. The SiN isolation layer is located between the source electrode and the Schottky contact gate electrode and between the Schottky contact gate electrode and the drain electrode. The transistor can change the doping density and defect density of source-drain materials through adjusting the dosage and annealing time of ion injection, thereby optimizing the spinning polarizability of the drain region and the source region under room temperature.

Description

Heterojunction high electron mobility spin fet and manufacture method
Technical field
The present invention relates to a kind of heterojunction high electron mobility spin fet and manufacture method, particularly relate to a kind of utilization and heterojunction high electron mobility spin fet and the manufacture method that source-drain electrode injects reception spinning polarized electron is made to tool defective 3C-SiC doping nitrogen-atoms.
Background technology
Along with the rapid renewal of modern electronic technology, no matter the development of conventional electronics, be the integrated or arithmetic speed aspect of scale, all seriously limit microelectronics the reach of science.Emerging spintronics is to regulate and control electron spin easily for main target, open the frontier in order to realizing information storage and transmission with electron spin, cause physics, the common concern of researcher and broad interest in many scientific domains such as materialogy and electronic informatics.
In recent years, based on the spin field effect pipe that two-dimensional electron gas proposes, its theoretical and experimental study relate to electron spin and transports and the complicated factor of many-sided impact such as material behavior, causes concern and the exploration of numerous researchers.Its basic conception is propose so-called spin traps transistor by the electrical type ratio of electrooptic modulator.The electron spin inputted by source electrode in the x-direction, it can be expressed as the combination of positive and negative automatic rotary component in the z-direction, the electron energy certainly spinning up and the spin downward division caused by the Rashba item in electron effective mass Hamilton, the phase difference of electronics by field effect transistor is produced in transport process, the electronic phase angle can regarded as along the spin of positive and negative z direction spinned in the x-direction received in drain electrode changes, thus carries out current regulation.And the Rashba coefficients R ashba coefficient η in Rashba item is directly proportional to the electric field of heterojunction boundary, therefore size of current can be controlled by adding grid voltage.
But spinning electron is injected in semiconductor by ferromagnetic material by general spin fet, but only has a few percent as Fe and semi-conducting material do not mate as the band structure of Sm the efficiency injected that makes to spin due to ferromagnetic material.Therefore, adopt identical source-drain electrode and channel material make band structure mate thus improve injection efficiency particularly important at the application and research of spin fet device.
N-type doping point defect 3C-SiC material has certain Spin Polarization Effect, can substitute existing technique, improve the efficiency that spin is injected and received, thus improve the performance of device.
Summary of the invention
The object of the invention is the defect for prior art, a kind of heterojunction high electron mobility spin fet and manufacture method are provided.Material spin polarizability at room temperature can be optimized.
For achieving the above object, the invention provides a kind of heterojunction high electron mobility spin fet, comprising: 3C-SiC drain region, 3C-SiC source region, 3C-SiC channel region, Schottky contacts gate electrode, Si substrate, drain electrode, source electrode, SiN separator;
Described 3C-SiC drain region, 3C-SiC source region, 3C-SiC channel region are positioned on described Si substrate; Described source electrode is positioned on described 3C-SiC source region, and described Schottky contacts gate electrode is positioned on described 3C-SiC channel region, and described drain electrode is positioned on described 3C-SiC drain region; Described SiN separator is positioned at source electrode and Schottky contacts gate electrode, and between Schottky contacts gate electrode and drain electrode.
Further, the material in described 3C-SiC drain region is N-type doping content is 1 × 10 17cm -3-1 × 10 20cm -3the defective 3C-SiC material of tool, thickness is 0.5 μm.
Further, the material in described 3C-SiC source region is N-type doping content is 1 × 10 17cm -3-1 × 10 20cm -3the defective 3C-SiC material of tool, thickness is 0.5 μm.
Further, described 3C-SiC channel region is 1 × 10 by N-type doping content 15-1 × 10 17cm -3epitaxial loayer is formed.
Further, the Ni Schottky contacts gate electrode of described Schottky contacts gate electrode to be the thickness formed by deposit be 300nm.
Further, described Si substrate is doping content is 1 × 10 14cm -3si material.
Present invention also offers a kind of manufacture method of heterojunction high electron mobility spin fet, described method comprises:
Step 1, uses acetone, absolute ethyl alcohol and deionized water to carry out ultrasonic cleaning to Si substrate successively;
Step 2, the on a si substrate lightly doped 3C-SiC epitaxial loayer of chemical vapour deposition (CVD) 0.5 μm, doping content is 1 × 10 15-1 × 10 17cm -3; Reaction temperature is 1570 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and impurity source adopts gaseous nitrogen atmosphere;
Four Nitrogen ion Selective implantations are formed drain region and source region by step 3:
Step 4, carries out gluing, development to whole silicon carbide epitaxial layers, above source region and drain region, form ohmic contact regions, the Ni metal of deposit 300nm, is peeled off afterwards make it form source electrode and drain metal layer by ultrasonic wave; In the argon gas atmosphere of 1100 DEG C, whole sample is annealed 3 minutes, form source, leak Ohm contact electrode;
Step 5, utilizes the plasma enhanced CVD method SiN layer that deposit 200nm is thick above epitaxial loayer, uses photoetching and CF afterwards 4plasma etching goes out the grid region of 1 μm;
Step 6, utilizes the method for magnetron sputtering at 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky contacts gate electrode, then short annealing process in argon gas atmosphere.
Further, described step 3 specifically comprises:
Step 31, on silicon carbide epitaxial layers deposit a layer thickness be the Al of 1 μm as the barrier layer of drain region and source region ion implantation, form drain region and injection region, source region by photoetching and etching;
Step 32, carries out four N~+ implantation to silicon carbide epitaxial layers, successively adopts the Implantation Energy of 200keV, 140keV, 100keV and 65keV, be injected into silicon carbide epitaxial layers at the temperature of 500 DEG C, and Formation Depth is 0.5 μm, and doping content is 1 × 10 17cm -3-1 × 10 20cm -3drain region and source region;
Step 33, adopts the Al on phosphoric acid removal silicon carbide epitaxial layers;
Step 34, adopts RCA standard of cleaning to clean silicon carbide epitaxial layers surface, makes the protection of C film after drying; And then in 850 DEG C of argon atmospheres, carry out ion-activated annealing 10min.
Heterojunction high electron mobility spin fet of the present invention and manufacture method, by regulating the dosage of ion implantation and annealing time to change doping content in source and drain material and defect concentration, thus the spin polarizability of material under optimizing room temperature.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of heterojunction high electron mobility spin fet of the present invention;
Fig. 2 is the flow chart of the manufacture method of heterojunction high electron mobility spin fet of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the schematic diagram of heterojunction high electron mobility spin fet of the present invention, as shown in the figure, 3C-SiC drain region 1,3C-SiC source region 2,3C-SiC channel region 3, Schottky contacts gate electrode 4, Si substrate 5, drain electrode 6, source electrode 7 and SiN separator 8 is specifically comprised.
3C-SiC drain region 1,3C-SiC source region 2,3C-SiC channel region 3 are positioned on Si substrate 5; Source electrode 7 is positioned on 3C-SiC source region 2, and Schottky contacts gate electrode 4 is positioned on 3C-SiC channel region 3, and drain electrode 6 is positioned on 3C-SiC drain region 1; SiN separator 8 is positioned at source electrode 7 and Schottky contacts gate electrode 4, and between Schottky contacts gate electrode 4 and drain electrode 6.
Wherein, 3C-SiC drain region 1 and 3C-SiC source region 2 are thickness is 0.5 μm, and N-type doping content is 1 × 10 17cm -3-1 × 10 20cm -3, preferably 1 × 10 19cm -3, there is the 3C-SiC material of defects, formed by three times or four Nitrogen ion selectivity ion implantations; 3C-SiC channel region 3 is 1 × 10 by N-type doping content 15-1 × 10 17cm -3epitaxial loayer is formed.The Ni Schottky contacts grid 4 of to be the thickness formed by deposit above 3C-SiC channel region 3 be 300nm; Drain electrode 6 and source electrode 7 are positioned at above drain region 1 and source region 2, are formed by the Ni of deposit 300nm, SiN as separator at Schottky contacts grid 4 and source electrode 6 with drain between 7, the generation of using plasma chemical vapor deposition.
Si substrate 5 is doping contents is 1 × 10 14cm -3si material.
Heterojunction high electron mobility spin fet of the present invention changes doping content in source and drain material and defect concentration by regulating the dosage of ion implantation and annealing time, thus optimizes material spin polarizability at room temperature.
Fig. 2 is the flow chart of the manufacture method of heterojunction high electron mobility spin fet of the present invention, as shown in the figure, specifically comprises the steps:
Step 1, uses acetone, absolute ethyl alcohol and deionized water to carry out ultrasonic cleaning to Si substrate successively;
Step 2, growth thickness is 0.5 μm of lightly doped 3C-SiC epitaxial loayer on a si substrate, and doping content is 1 × 10 15-1 × 10 17cm -3, its process conditions are: reaction temperature is 1570 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and impurity source adopts gaseous nitrogen atmosphere;
Step 3, four times Nitrogen ion Selective implantation forms drain region and source region:
Concrete, comprising: step 3.1, on silicon carbide epitaxial layers deposit a layer thickness be the Al of 1 μm as the barrier layer of drain region and source region ion implantation, form drain region and injection region, source region by photoetching and etching;
Step 3.2, carries out four N~+ implantation to silicon carbide epitaxial layers, successively adopts the Implantation Energy of 200keV, 140keV, 100keV and 65keV, be injected into silicon carbide epitaxial layers at the temperature of 500 DEG C, and Formation Depth is 0.5 μm, and doping content is 1 × 10 17cm -3-1 × 10 20cm -3drain region and source region;
Step 3.3, adopts the Al on phosphoric acid removal silicon carbide epitaxial layers;
Step 3.4, adopts RCA standard of cleaning to clean silicon carbide epitaxial layers surface, makes the protection of C film after drying; Then in 850 DEG C of argon atmospheres, carry out ion-activated annealing 10min.
Step 4, carries out gluing, development to whole silicon carbide epitaxial layers, above source region and drain region, form ohmic contact regions, the Ni metal of deposit 300nm, is peeled off afterwards make it form source electrode and drain metal layer by ultrasonic wave; In the argon gas atmosphere of 1100 DEG C, whole sample is annealed 3 minutes, form source, leak Ohm contact electrode;
Specifically comprise:
Step 4.1, carries out gluing, development to whole silicon carbide epitaxial layers, above source region and drain region, form ohmic contact regions, the Ni metal of deposit 300nm, is peeled off afterwards make it form source electrode and drain metal layer by ultrasonic wave;
Step 4.2, in the argon gas atmosphere of 1100 DEG C, anneals 3 minutes to whole sample, forms source, leaks Ohm contact electrode;
Step 5, utilizes the plasma enhanced CVD method SiN layer that deposit 200nm is thick above epitaxial loayer, uses photoetching and CF afterwards 4plasma etching goes out the grid region of 1 μm;
Step 6, utilizes the method for magnetron sputtering at 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky contacts gate electrode, then short annealing process in argon gas atmosphere.
Heterojunction high electron mobility spin fet manufacture method of the present invention, because raceway groove and source and drain adopt commaterial, directly can carry out epitaxial growth on substrate, source and drain adopts the mode of selected zone ion implantation nitrogen-atoms to be formed simultaneously, have with common process compatible, manufacture simple, the advantage that skin effect is little, spin can be improved simultaneously and inject and receiving efficiency.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. a heterojunction high electron mobility spin fet, is characterized in that, comprising: 3C-SiC drain region, 3C-SiC source region, 3C-SiC channel region, Schottky contacts gate electrode, Si substrate, drain electrode, source electrode, SiN separator;
Described 3C-SiC drain region, 3C-SiC source region, 3C-SiC channel region are positioned on described Si substrate; Described source electrode is positioned on described 3C-SiC source region, and described Schottky contacts gate electrode is positioned on described 3C-SiC channel region, and described drain electrode is positioned on described 3C-SiC drain region; Described SiN separator is positioned at source electrode and Schottky contacts gate electrode, and between Schottky contacts gate electrode and drain electrode.
2. heterojunction high electron mobility spin fet according to claim 1, is characterized in that, the material in described 3C-SiC drain region is N-type doping content is 1 × 10 17cm -3-1 × 10 20cm -3the defective 3C-SiC material of tool, thickness is 0.5 μm.
3. heterojunction high electron mobility spin fet according to claim 1, is characterized in that, the material in described 3C-SiC source region is N-type doping content is 1 × 10 17cm -3-1 × 10 20cm -3the defective 3C-SiC material of tool, thickness is 0.5 μm.
4. heterojunction high electron mobility spin fet according to claim 1, is characterized in that, described 3C-SiC channel region is 1 × 10 by N-type doping content 15-1 × 10 17cm -3epitaxial loayer is formed.
5. heterojunction high electron mobility spin fet according to claim 1, is characterized in that, the Ni Schottky contacts gate electrode of described Schottky contacts gate electrode to be the thickness formed by deposit be 300nm.
6. heterojunction high electron mobility spin fet according to claim 1, is characterized in that, described Si substrate is N-type doping content is 1 × 10 14cm -3si material.
7. a manufacture method for heterojunction high electron mobility spin fet, is characterized in that, described method comprises:
Step 1, uses acetone, absolute ethyl alcohol and deionized water to carry out ultrasonic cleaning to Si substrate successively;
Step 2, chemical vapour deposition (CVD) thickness is 0.5 μm of lightly doped 3C-SiC epitaxial loayer on a si substrate, and doping content is 1 × 10 15-1 × 10 17cm -3; Reaction temperature is 1570 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and impurity source adopts gaseous nitrogen atmosphere;
Nitrogen ion four Selective implantations are formed drain region and source region by step 3:
Step 4, carries out gluing, development to whole silicon carbide epitaxial layers, above source region and drain region, form ohmic contact regions, the Ni metal of deposit 300nm, is peeled off afterwards make it form source electrode and drain metal layer by ultrasonic wave; In the argon gas atmosphere of 1100 DEG C, whole sample is annealed 3 minutes, form source, leak Ohm contact electrode;
Step 5, utilizes the plasma enhanced CVD method SiN layer that deposit 200nm is thick above epitaxial loayer, uses photoetching and CF afterwards 4plasma etching goes out the grid region of 1 μm;
Step 6, utilizes the method for magnetron sputtering at 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky contacts gate electrode, then short annealing process in argon gas atmosphere.
8. method according to claim 7, is characterized in that, described step 3 specifically comprises:
Step 31, on silicon carbide epitaxial layers deposit a layer thickness be the Al of 1 μm as the barrier layer of drain region and source region ion implantation, form drain region and injection region, source region by photoetching and etching;
Step 32, carries out four N~+ implantation to silicon carbide epitaxial layers, successively adopts the Implantation Energy of 200keV, 140keV, 100keV and 65keV, be injected into silicon carbide epitaxial layers at the temperature of 500 DEG C, and Formation Depth is 0.5 μm, and doping content is 1 × 10 17cm -3-1 × 10 20cm -3drain region and source region;
Step 33, adopts the Al on phosphoric acid removal silicon carbide epitaxial layers;
Step 34, adopts RCA standard of cleaning to clean silicon carbide epitaxial layers surface, makes the protection of C film after drying; Then in 850 DEG C of argon atmospheres, carry out ion-activated annealing 10min.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107359127A (en) * 2017-06-07 2017-11-17 西安电子科技大学 The Fe doping spin fets and its manufacture method of Sapphire Substrate
CN108735849A (en) * 2017-04-18 2018-11-02 上海新昇半导体科技有限公司 A kind of photoconductive switch and preparation method thereof

Citations (4)

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Publication number Priority date Publication date Assignee Title
US5270554A (en) * 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
CN1441965A (en) * 2000-05-10 2003-09-10 克里公司 Silicon carbide metal-semiconductor field effect transistors and methods of fabricating silicon carbide metal-semiconductor field effect transistors
CN101536192A (en) * 2006-11-10 2009-09-16 住友电气工业株式会社 Silicon carbide semiconductor device and process for producing the same
CN103730359A (en) * 2013-10-09 2014-04-16 西安电子科技大学 Manufacturing method of composite gate media SiC MISFET

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270554A (en) * 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
CN1441965A (en) * 2000-05-10 2003-09-10 克里公司 Silicon carbide metal-semiconductor field effect transistors and methods of fabricating silicon carbide metal-semiconductor field effect transistors
CN101536192A (en) * 2006-11-10 2009-09-16 住友电气工业株式会社 Silicon carbide semiconductor device and process for producing the same
CN103730359A (en) * 2013-10-09 2014-04-16 西安电子科技大学 Manufacturing method of composite gate media SiC MISFET

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735849A (en) * 2017-04-18 2018-11-02 上海新昇半导体科技有限公司 A kind of photoconductive switch and preparation method thereof
CN107359127A (en) * 2017-06-07 2017-11-17 西安电子科技大学 The Fe doping spin fets and its manufacture method of Sapphire Substrate
CN107359127B (en) * 2017-06-07 2020-03-24 西安电子科技大学 Fe-doped spin field effect transistor of sapphire substrate and manufacturing method thereof

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