CN105789047B - A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor - Google Patents
A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor Download PDFInfo
- Publication number
- CN105789047B CN105789047B CN201610318436.4A CN201610318436A CN105789047B CN 105789047 B CN105789047 B CN 105789047B CN 201610318436 A CN201610318436 A CN 201610318436A CN 105789047 B CN105789047 B CN 105789047B
- Authority
- CN
- China
- Prior art keywords
- layer
- gan
- aln
- algan
- vacancies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910002704 AlGaN Inorganic materials 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 230000006911 nucleation Effects 0.000 claims description 8
- 238000010899 nucleation Methods 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims description 2
- 230000037431 insertion Effects 0.000 claims description 2
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 7
- 238000005036 potential barrier Methods 0.000 abstract 2
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides a kind of enhanced AlGaN/GaN high electron mobility transistor preparation methods, method successively grows GaN or AlN nucleating layer, GaN buffer layer, GaN channel layer, AlN insert layer, AlGaN potential barrier and InGaN cap layers on a substrate, and source electrode and drain electrode is made in AlGaN potential barrier, and grid is made in InGaN cap layers, obtain enhanced AlGaN/GaN high electron mobility transistor.InGaN cap layers in the present invention contain a large amount of vacancy In, since a large amount of presence in the vacancy In can adsorb electronics, electronegativity is presented in entire cap layers, in this way raise barrier layer conduction level, to exhaust the two-dimensional electron gas of channel, it realizes the enhanced of device, and avoids the difficult point of traditional p-type cap layers high concentration p doping relatively difficult to achieve, enhance the operability of device preparation.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a preparation method of an enhanced AlGaN/GaN High Electron Mobility Transistor (HEMT).
Background
GaN has become a current research hotspot as a third generation wide bandgap semiconductor material. GaN has the characteristics of large forbidden band width, high critical breakdown electric field, high electron saturation drift rate and the like, and has unique advantages in the aspect of preparing semiconductor power devices with high power, high frequency, high speed and small volume.
Due to the spontaneous polarization effect and piezoelectric polarization effect of the GaN-based power electronic device represented by AlGaN/GaN, a large amount of two-dimensional electron gas can be generated at a heterojunction interface, the concentration of the two-dimensional electron gas can reach 1013cm & lt-2 & gt magnitude, and the electron mobility is 2000cm2More than V.s. Due to the characteristics, the AlGaN/GaN-based power device has the advantages of high current density, low on-resistance, high power density and the like. The method has wide application prospect in the power electronic fields of battery management, wind power generation, solar batteries, electric vehicles and the like.
Since AlGaN/GaN power electronic devices are typically depletion mode devices, this adds power consumption and complexity to the circuit design. Meanwhile, in power electronic application, the safety of circuit operation is greatly reduced due to the normally open characteristic of the circuit, and serious potential safety hazard exists due to the lack of a self-protection mechanism under the condition of grid failure. Based on the above drawbacks, the enhanced high electron mobility device has been the focus and hot spot of research.
Aiming at the research of the enhancement device, at present, methods of etching a concave grid, injecting fluorine ions, growing a p-GaN or p-AlGaN cap layer and the like are generally adopted to deplete two-dimensional electron gas of a channel below the grid. However, these methods have large defects in process and device performance, for example, the recessed gate etching process is difficult to control accurately, and the introduced etching damage is large, which may cause current collapse and deteriorate the reliability of the device; fluorine ion implantation also presents a number of stability problems; due to the self-compensation effect and high activation energy of acceptor impurities, the doping efficiency of acceptor doped atoms is low, and the growth of the P-type cap layer with high doping concentration is difficult to realize.
Disclosure of Invention
Technical problem to be solved
The invention aims to provide a preparation method of an enhanced AlGaN/GaN high electron mobility transistor, which realizes the enhanced AlGaN/GaN high electron mobility transistor and has the advantages of controllable process, small etching damage and high device process reliability.
(II) technical scheme
The invention provides a preparation method of an enhanced AlGaN/GaN high electron mobility transistor, which comprises the following steps:
s1, growing a GaN or AlN low-temperature nucleation layer on a substrate;
s2, growing a GaN buffer layer on the GaN or AlN nucleation layer;
s3, growing a GaN channel layer on the GaN buffer layer;
s4, growing an AlN insert layer on the GaN channel layer;
s5, growing an AlGaN barrier layer on the AlN insert layer;
s6, growing an InGaN cap layer on the partial surface area of the AlGaN barrier layer, wherein the InGaN cap layer contains In vacancies;
and S7, respectively manufacturing a source electrode and a drain electrode in a region where the InGaN cap layer does not grow on the surface of the AlGaN barrier layer, and manufacturing a grid electrode on the InGaN cap layer.
(III) advantageous effects
The InGaN cap layer contains a large number of In vacancies, and because a large number of In vacancies can adsorb electrons, the whole cap layer presents electronegativity, so that the conduction band energy level of the barrier layer is raised, two-dimensional electron gas of a channel is exhausted, enhancement of a device is realized, the difficulty that high-concentration P doping is difficult to realize by the traditional P-type cap layer is avoided, and the operability of device preparation is enhanced.
Drawings
FIG. 1 is a schematic diagram of an enhanced AlGaN/GaN high electron mobility transistor made in accordance with the present invention.
Fig. 2 is a flowchart of a method for manufacturing an enhanced AlGaN/GaN high electron mobility transistor according to the present invention.
Detailed Description
The invention provides a preparation method of an enhanced AlGaN/GaN high electron mobility transistor, which comprises the steps of growing a GaN or AlN nucleating layer, a GaN buffer layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and an InGaN cap layer containing In vacancies on a substrate In sequence, manufacturing a source electrode and a drain electrode on the AlGaN barrier layer, and manufacturing a grid electrode on the InGaN cap layer to obtain the enhanced AlGaN/GaN high electron mobility transistor. The InGaN cap layer contains a large number of In vacancies, and because a large number of In vacancies can adsorb electrons, the whole cap layer presents electronegativity, so that the conduction band energy level of the barrier layer is raised, two-dimensional electron gas of a channel is exhausted, enhancement of a device is realized, the difficulty that high-concentration P doping is difficult to realize by the traditional P-type cap layer is avoided, and the operability of device preparation is enhanced.
Fig. 2 is a flowchart of a method for manufacturing an enhancement AlGaN/GaN high electron mobility transistor according to the present invention, and as shown in fig. 2, the method includes:
s1, growing a GaN or AlN low-temperature nucleation layer on a substrate;
s2, growing a GaN buffer layer on the GaN or AlN nucleation layer;
s3, growing a GaN channel layer on the GaN buffer layer;
s4, growing an AlN insert layer on the GaN channel layer;
s5, growing an AlGaN barrier layer on the AlN insert layer;
s6, growing an InGaN cap layer on the partial surface area of the AlGaN barrier layer, wherein the InGaN cap layer contains In vacancies;
s7, respectively manufacturing a source electrode and a drain electrode in a region where the InGaN cap layer does not grow on the surface of the AlGaN barrier layer, and manufacturing a grid electrode on the InGaN cap layer;
s8, depositing Ti/Al/Ti/Au or Ti/Al/Ni/Au on the source electrode and the drain electrode, and annealing the source electrode and the drain electrode to form ohmic contact; Ni/Au is deposited on the gate and the gate is annealed to form a Schottky contact.
Further, step S6 includes:
s61, depositing a SiO layer on the AlGaN barrier layer2A layer;
s62, to SiO2Etching the layer to expose partial surface of the AlGaN barrier layer, wherein the etching comprises the specific steps of coating glue, exposing, developing, fixing a film and etching;
and S63, growing an InGaN cap layer containing In vacancies on the exposed partial region of the surface of the AlGaN barrier layer.
Further, in step S61, SiO is deposited by PECVD2Layer of, among them, SiO2The thickness of the layer is 100-200nm, and the deposition temperature is 200-400 ℃.
Further, In step S63, an InGaN cap layer containing In vacancies is periodically grown by alternately performing low temperature growth and high temperature annealing, wherein the growth thickness of each period is 5 to 10nm, and the total thickness of the InGaN cap layer is 50 to 150 nm.
Further, the low-temperature growth temperature of the InGaN cap layer containing the In vacancies is 700-800 ℃, the high-temperature annealing temperature is 900-1000 ℃, and the high-temperature annealing time In each period is 5-10 min.
Further, in step S7, before the source and the drain are formed on the surface of the AlGaN barrier layer, the remaining SiO on the AlGaN barrier layer is removed by wet etching2And (3) a layer.
Further, epitaxial growth is carried out by adopting a metal organic chemical vapor deposition method to grow a GaN or AlN nucleating layer, a GaN buffer layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and an InGaN cap layer containing In vacancies, and the method specifically comprises the following steps:
setting the temperature between 500 ℃ and 600 ℃, adjusting the pressure between 300 ℃ and 600Torr, and growing a low-temperature GaN or AlN nucleation layer with the thickness of 10-150 nm;
raising the temperature to 900-1100 ℃, reducing the pressure to 50-200Torr, and growing a C self-doped semi-insulating high-resistance GaN layer with the thickness of 2-3 μm;
adjusting the temperature to 1000-;
the temperature is adjusted to 800-1050 ℃, the pressure is adjusted to 50-100Torr, and an AlN doped layer is grown with a thickness of 1-3 nm.
The temperature is adjusted to 800-1050 ℃, the pressure is adjusted to 50-100Torr, an AlGaN barrier layer is grown, the thickness is 10-30nm, and the Al component is 15-30%.
Furthermore, the substrates adopted by the invention are sapphire, silicon carbide or silicon substrates.
Fig. 1 is a schematic view of an AlGaN/GaN high electron mobility transistor manufactured according to the present invention, as shown in fig. 1, the AlGaN/GaN high electron mobility transistor is sequentially grown with a GaN or AlN nucleation layer, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and an InGaN cap layer on a substrate from bottom to top, the AlGaN barrier layer is further respectively manufactured with a source and a drain, and the InGaN cap layer is manufactured with a gate. The InGaN cap layer contains a large number of In vacancies, because the InGaN material grows at a relatively low temperature, because atomic bond energy between In and N is weak, when the temperature is increased, In atoms are easy to volatilize to form In vacancies, after the In vacancies are formed, the nearest atoms of the vacancies respectively have an unpaired electron to become unsaturated covalent bonds, and the bonds tend to accept the electron, so that the In vacancies present the property of acceptor impurities In the bulk material. Thus, a thicker InGaN cap layer containing a large number of In vacancies is grown by a growth process repeated by a low-temperature growth high-temperature annealing cycle. Because a large number of In vacancies exist In the cap layer, electrons can be adsorbed, and the whole cap layer presents electronegativity, so that the energy level of a conduction band of the barrier layer is raised, two-dimensional electron gas of a channel is exhausted, and the enhancement of the device is realized.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings in combination with specific embodiments.
1. Cleaning a sapphire, silicon carbide or silicon substrate, putting the cleaned sapphire, silicon carbide or silicon substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) system, raising the temperature to between 500 ℃ and 600 ℃, adjusting the pressure to between 300 ℃ and 600Torr, and growing a low-temperature GaN or AlN nucleating layer with the thickness of 10-150 nm.
2. The temperature is increased to 900-1100 ℃, the pressure is reduced to 50-200Torr, and the C self-doped semi-insulating high-resistance GaN layer grows to 2-3 μm.
3. The temperature is adjusted to 1000-1200 ℃ and the pressure is adjusted to 200-500Torr, and a GaN channel layer with high mobility is grown by 10-100 nm.
4. The temperature is adjusted to 800-1050 ℃, the pressure is adjusted to 50-100Torr, and an AlN insert layer is grown with the thickness of 1-3 nm.
5. The temperature is adjusted to 800-1050 ℃, the pressure is adjusted to 50-100Torr, an AlGaN barrier layer is grown, the thickness is 10-30nm, and the Al component is 15-30%.
6. The grown structure is placed into a PECVD furnace, and a layer of SiO with the thickness of 100-200nm is deposited at the temperature of 200-400 DEG C2And (3) a layer.
7. Gluing, exposing, developing, film fixing and etching are carried out on the device deposited with the SiO2 layer, and holes are formed in the gate region of the HEMT, so that a SiO2 mask is left except the gate region.
8. And placing the device into an MOCVD system for secondary epitaxy, and growing an InGaN cap layer containing a large number of In vacancies. The method comprises the steps of firstly raising the temperature to 700-800 ℃, introducing an In source and a Ga source, growing a cap layer with the thickness of about 5-10nm at the temperature, then raising the temperature to 900-1000 ℃, keeping the temperature for 5-10min to ensure that In atoms In the grown InGaN thin layer are fully volatilized to form In vacancies, then lowering the temperature back to the growth temperature of the InGaN layer for growth, and repeating the steps to ensure that the total thickness of the grown InGaN cap layer with a large number of In vacancies reaches about 50-150 nm.
9. And removing the SiO2 layer on the surface of the device except the gate region by adopting a wet etching process.
10. Ti/Al/Ti/Au or Ti/Al/Ni/Au is deposited on the source electrode area and the drain electrode area of the HEMT device, Ni/Au is deposited on the grid electrode area, and ohmic contact and Schottky contact are formed after annealing respectively.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A preparation method of an enhanced AlGaN/GaN high electron mobility transistor is characterized by comprising the following steps:
s1, growing a GaN or AlN low-temperature nucleation layer on a substrate;
s2, growing a GaN buffer layer on the GaN or AlN nucleating layer;
s3, growing a GaN channel layer on the GaN buffer layer;
s4, growing an AlN insert layer on the GaN channel layer;
s5, growing an AlGaN barrier layer on the AlN insert layer;
s6, growing an InGaN cap layer on the partial surface area of the AlGaN barrier layer, wherein the InGaN cap layer contains In vacancies, and the whole cap layer presents electronegativity due to the fact that electrons can be adsorbed by the In vacancies;
s7, respectively manufacturing a source electrode and a drain electrode in a region where the InGaN cap layer does not grow on the surface of the AlGaN barrier layer, and manufacturing a grid electrode on the InGaN cap layer; wherein,
the step S6 includes:
s61, depositing a SiO layer on the AlGaN barrier layer2A layer;
s62, for the SiO2Etching the layer to expose partial surface area of the AlGaN barrier layer;
and S63, growing an InGaN cap layer containing In vacancies on the exposed partial region of the surface of the AlGaN barrier layer.
2. The method of claim 1, wherein the SiO is deposited by PECVD in step S612Layer, wherein, the SiO2The thickness of the layer is 100-200nm, and the deposition temperature is 200-400 ℃.
3. The method of claim 1, wherein In step S63, the InGaN cap layer containing In vacancies is periodically grown by alternately performing low temperature growth and high temperature annealing, wherein the growth thickness of each period is 5-10nm, and the total thickness of the InGaN cap layer containing In vacancies is 50-150 nm.
4. The method of claim 3, wherein the InGaN cap layer containing In vacancies grows at a low temperature of 700-.
5. The method of claim 1, wherein in step S7, before forming a source and a drain on the surface of the AlGaN barrier layer, wet etching is used to remove the remaining SiO on the AlGaN barrier layer2And (3) a layer.
6. The method of claim 1, further comprising:
s8, depositing Ti/Al/Ti/Au or Ti/Al/Ni/Au on the source electrode and the drain electrode, and annealing the source electrode and the drain electrode to form ohmic contact; depositing Ni/Au on the grid electrode, and annealing the grid electrode to form a Schottky contact.
7. The method of claim 1, wherein the epitaxial growth is performed by metal organic chemical vapor deposition to grow the GaN or AlN nucleation layer, the GaN buffer layer, the GaN channel layer, the AlN insertion layer, the AlGaN barrier layer, and the InGaN cap layer containing In vacancies.
8. The method of claim 1, wherein the first and second electrodes are formed on a substrate,
the thickness of the GaN or AlN nucleating layer is 10-150 nm;
the thickness of the GaN buffer layer is 2-3 mu m;
the thickness of the GaN channel layer is 10-100 nm;
the thickness of the AlN insert layer is 1-3 nm;
the AlGaN barrier layer is 10-30nm thick, and the content of Al is 15% -30%.
9. The method of claim 1, wherein the substrate is one of sapphire, silicon carbide or silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610318436.4A CN105789047B (en) | 2016-05-13 | 2016-05-13 | A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610318436.4A CN105789047B (en) | 2016-05-13 | 2016-05-13 | A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105789047A CN105789047A (en) | 2016-07-20 |
| CN105789047B true CN105789047B (en) | 2018-12-18 |
Family
ID=56379704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610318436.4A Active CN105789047B (en) | 2016-05-13 | 2016-05-13 | A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105789047B (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601787B (en) * | 2016-12-01 | 2020-06-26 | 北京大学 | InxAlyGa1-x-yN/GaN heterostructure and epitaxial method thereof |
| JP6685890B2 (en) * | 2016-12-19 | 2020-04-22 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| CN107887435A (en) * | 2017-11-28 | 2018-04-06 | 中国科学院半导体研究所 | Enhanced GaN HEMT preparation method |
| CN109659363A (en) * | 2018-11-20 | 2019-04-19 | 西安电子科技大学芜湖研究院 | A kind of preparation method of the low ohm contact structures of gallium nitride HEMT structure |
| CN109585544A (en) * | 2018-11-20 | 2019-04-05 | 西安电子科技大学芜湖研究院 | A kind of structure and preparation method thereof based on the enhanced HEMT device low resistance Ohmic contact of gallium nitride |
| CN109638071A (en) * | 2018-11-20 | 2019-04-16 | 西安电子科技大学芜湖研究院 | A kind of structure and preparation method thereof based on Si underlayer nitriding gallium HEMT low resistance Ohmic contact |
| CN109659362A (en) * | 2018-11-20 | 2019-04-19 | 西安电子科技大学芜湖研究院 | A kind of structure and preparation method thereof based on the low ohm contact resistance of gallium nitride power HEMT structure |
| CN111384163A (en) * | 2018-12-28 | 2020-07-07 | 中国科学院半导体研究所 | Structure and layout for improving heat dissipation performance of GaN HEMT device |
| CN110034174A (en) * | 2019-02-28 | 2019-07-19 | 华灿光电(苏州）有限公司 | High electron mobility transistor epitaxial wafer and preparation method thereof |
| CN110335804A (en) * | 2019-04-17 | 2019-10-15 | 中国科学院半导体研究所 | A kind of growing method of InGaN film |
| CN110767746A (en) * | 2019-10-28 | 2020-02-07 | 北京华进创威电子有限公司 | HEMT structure with in-situ grown dielectric layer as cap layer and manufacturing method thereof |
| CN110767747A (en) * | 2019-10-28 | 2020-02-07 | 北京华进创威电子有限公司 | Enhanced GaN-based high electron mobility transistor material structure |
| CN111463260B (en) * | 2020-03-10 | 2022-09-13 | 安徽长飞先进半导体有限公司 | Vertical high electron mobility field effect transistor and preparation method thereof |
| CN111952365A (en) * | 2020-08-14 | 2020-11-17 | 中国科学院半导体研究所 | Carbon-doped and controlled GaN-based HEMT epitaxial structure and manufacturing method thereof |
| CN113964192A (en) * | 2021-09-06 | 2022-01-21 | 西安电子科技大学 | Non-polar GaN-based Schottky diode and preparation method thereof |
| WO2024060083A1 (en) * | 2022-09-21 | 2024-03-28 | 华为技术有限公司 | Semiconductor device and manufacturing method therefor, and electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103930995A (en) * | 2011-11-22 | 2014-07-16 | 德州仪器公司 | Enhancement-mode group III-n high electronic mobility transistor with reverse polarization cap |
-
2016
- 2016-05-13 CN CN201610318436.4A patent/CN105789047B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103930995A (en) * | 2011-11-22 | 2014-07-16 | 德州仪器公司 | Enhancement-mode group III-n high electronic mobility transistor with reverse polarization cap |
Non-Patent Citations (2)
| Title |
|---|
| AlGaN/GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation;T.Mizutani ect.;《Electron Device Letters》;20070731;第28卷(第7期);第549-550页 * |
| MOCVD grown normally-OFF type AlGaN/GaN HEMTs on 4 inch Si using p-InGaN cap layer with high breakdown;S. Lawrence Selvaraj etc.;《 68th Device Research Conference》;20100623;第135-136页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105789047A (en) | 2016-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105789047B (en) | A kind of preparation method of enhanced AlGaN/GaN high electron mobility transistor | |
| US9269577B2 (en) | Method for manufacturing nitride semiconductor device | |
| CN101252088B (en) | Realizing method of novel enhancement type AlGaN/GaN HEMT device | |
| CN109873034B (en) | Normally-off HEMT power device for depositing polycrystalline AlN and preparation method thereof | |
| CN113380623A (en) | Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation | |
| CN111223777B (en) | GaN-based HEMT device and manufacturing method thereof | |
| CN110459595A (en) | A kind of enhanced AlN/AlGaN/GaN HEMT device and preparation method thereof | |
| CN109037326A (en) | A kind of enhanced HEMT device and preparation method thereof with p type buried layer structure | |
| CN106876443A (en) | GaN high electron mobility transistor of high-breakdown-voltage and forming method thereof | |
| CN111384171A (en) | High-channel mobility vertical UMOSFET device and preparation method thereof | |
| CN210429824U (en) | Enhanced AlN/AlGaN/GaN HEMT device | |
| CN112018176A (en) | Semiconductor device and manufacturing method thereof | |
| CN110137244B (en) | Vertical-structure HEMT device with GaN-based self-supporting substrate and preparation method | |
| WO2021139041A1 (en) | Gallium oxide schottky diode and preparation method therefor | |
| CN108807500B (en) | Enhanced high electron mobility transistor with high threshold voltage | |
| CN111799326B (en) | Novel transistor structure for regulating and controlling two-dimensional electron gas concentration and manufacturing method | |
| CN112018177B (en) | Full-vertical Si-based GaN UMOSFET power device and preparation method thereof | |
| CN210092092U (en) | Magnesium-doped prepared enhanced GaN-based HEMT device | |
| CN210092091U (en) | Auxiliary doping realization normally-off GaN HEMT device | |
| CN110838514B (en) | Epitaxial structure of semiconductor device, preparation method of epitaxial structure and semiconductor device | |
| CN111682064A (en) | High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof | |
| CN109244131A (en) | A kind of high speed transistor and its manufacturing method | |
| CN114121656B (en) | Preparation method of novel HEMT device based on silicon substrate and device | |
| CN115732566A (en) | UMOSFET device and method for improving performance of UMOSFET device | |
| CN113725297B (en) | Normally open gallium oxide-based HFET device with cap layer and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |