CN105293428A - Full silicification wafer level vacuum encapsulation method and device for MEMS (Micro-Electro-Mechanical System) device - Google Patents
Full silicification wafer level vacuum encapsulation method and device for MEMS (Micro-Electro-Mechanical System) device Download PDFInfo
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Abstract
The invention relates to a full silicification wafer level vacuum encapsulation method and device for an MEMS (Micro-Electro-Mechanical System) device. Through adoption of a planar electrode leading-out scheme, vacuum sealing of the device is realized through a single sealing metal ring. An electrical signal leading-out way of a planar electrode is adopted, so that the common problem of introduction of large parasitic capacitance in an all-silicon wafer level encapsulation process is solved effectively. An electrical interconnection is realized through a silicon lead, so that an integral encapsulation process has a higher process compatibility temperature. Thus, an insulating medium layer with a higher density and higher quality can be prepared on the lead, thereby improving the machining yield and long-term use reliability of the device.
Description
Technical field:
The present invention relates to method for packing and the packaging of a kind of microelectromechanical systems (MEMS) device, particularly relate to a kind of full silicidation wafer-level encapsulation method and packaging of MEMS.
Background technology:
Many MEMS such as MEMS gyro instrument, MEMS resonator, mems accelerometer etc. all need to be operated in vacuum environment or low pressure airtight environment, to obtain high-quality-factor (Q value), larger detection bandwidth etc.But the cost of the Vacuum Package cost of shell level far super MEMS itself, the low cost requirement of MEMS can not be met.MEMS Wafer-Level Packaging Technology is a kind of MEMS package technology of low cost, utilizes the wafer bonding approach in MEMS technology to realize MEMS in the Vacuum Package of technique flow process or low pressure level Hermetic Package.Bonding techniques generally includes silicon-glass anodic bonding, gold silicon eutectic bonding, glass paste bonding, silicon-silicon bond conjunction etc.Anode linkage technology for disk encapsulation has the process program making glass block, as Southeast China University, still patent 200910262848.0,200910263297.X disclosed in the people such as Jintang have set forth silicon on glass bonding, and form the preparation scheme of wafer-level glass block in conjunction with hot mastication glass, and relevant Wafer-Level Packaging Technology.But this technology is comparatively complicated, cost is higher.The people (200710121384.2) such as Peking University's fourth great waves, and the people (201010279475.0) such as Beijing Space Age Optical Science & Technology Co., Ltd Zhang Tingkai individually discloses the wafer-level vacuum package scheme based on glass through hole, achieves the wafer-level vacuum package based on silicon on glass bonding.But above-mentioned two kinds of technical schemes, all need can realize airtight electrode leading-out terminal in the preparation of glass lead to the hole site.When the electrode of MEMS is more, the electrode as MEMS gyro instrument often reaches 8-10, and leading-out terminal will take a large amount of chip areas, be unfavorable for MEMS reduced volume, reduce costs.
Total silicon MEMS technology is the novel process technology based on total silicon bonding techniques.Compare total silicon bonding techniques with anode linkage and significantly reduce the temperature drift that MEMS causes due to material thermal mismatching, improve the stability of MEMS.MEMS Wafer-Level Packaging Technology based on total silicon bonding can either improve the performance of MEMS, can take into account again the low cost requirement of MEMS.No.13 Inst., Chinese Electronic Science & Technology Group Co Xu Yong green grass or young crops waits people to disclose a kind of total silicon MEMS wafer-level vacuum package technology 200910227989.9.This technical scheme makes V-type through hole on silicon cover plate, between MEMS structure sheet, realize mechanical connection by gold silicon eutectic bonding, is the signal of telecommunication extraction electrode of lower floor's silicon structure in the middle of cover plate V-type through hole.In order to ensure air-tightness, between V-type through hole and electrode, making sealed eyelet, having formed eutectic solder at AuSi wafer bonding technical process sealed eyelet and lower floor's silicon, achieving hermetically sealed to the cavity of MEMS.But this technology is the same with above-mentioned two silex glass Wafer-Level Packaging Technology, draws at electrode and air-tightness has made the person of needs and prepare around the larger chip area sacrifice of the sealing of pressure welding electrode surrounding, add the totle drilling cost of MEMS.
Silicon through hole (TSV) technology be another MEMS wafer level vacuum the solution of level Hermetic Package.TSV technology by preparing the metal electric connecting line of the series of processes preparations such as silicon through hole, through hole insulating, via metal by Vacuum Package silicon cover plate on silicon cover plate.Wafer-level vacuum package technology based on TSV technology has that volume is little, the technological merit of full silicidation, but this technical difficulty is large, processing cost is high, rely on expensive process equipment and technique, as prepared the through hole of break-through silicon chip by ICP etching and adopting atomic layer deposition (ALD) to prepare plating seed layer etc.In addition, adopt the ring-type insulator of break-through silicon chip in the total silicon disk encapsulation technology of TSV type, there is larger developed area, larger parasitic capacitance can be introduced between electrode, thus reduce the performance of MEMS, add the load of interface circuit.
Summary of the invention
Technical problem to be solved by this invention is to provide that a kind of cost is low, method simple MEMS full silicidation wafer-grade vacuum encapsulation method, effectively avoid the problem of the larger parasitic capacitance of introducing common in total silicon disk packaging technology, draw at electrode and shared chip area can be saved when realizing air-tightness, improve processed finished products rate and the long term reliability of device.
A full silicidation wafer-grade vacuum encapsulation method for MEMS, comprises the steps:
Prepare silicon cover plate; Described silicon cover plate comprises silicon substrate, silicon lead-in wire, insulating medium layer, weldering point contact electrode, pressure welding electrode and Vacuum Package solder ring, insulating medium layer is positioned at above silicon substrate, silicon lead-in wire is positioned at insulating medium layer inside, weldering point contact electrode is by contact solder joint through hole and silicon wire contacts, pressure welding electrode is by pressure welding electrode through hole and silicon wire contacts, and Vacuum Package solder ring is positioned at outside weldering point contact electrode; Preparation MEMS; Described MEMS comprises device substrate, MEMS structure, silicon anchor point, silicon sealing ring and SiO insulator; Silicon cover plate and MEMS are carried out eutectic bonding in vacuum pressure bonder and completes full silicidation wafer-level vacuum package, described Vacuum Package solder ring and silicon sealing ring generation eutectic reaction, thus silicon cover plate and MEMS are bonded together, form vacuum seal cavity, described MEMS structure sealing structure is in described vacuum seal cavity; Described weldering point contact electrode and silicon anchor point generation eutectic reaction, form machinery and be connected with electricity; The structural electric signal transmission of MEMS on corresponding silicon anchor point, then transfer to weldering point contact electrode on and by silicon lead-in wire and pressure welding electrode complete the signal of telecommunication extraction, pressure welding electrode is positioned at MEMS outside.The method preparing silicon cover plate is as follows: the process substrates forming silicon cover plate, and the process substrates of silicon cover plate comprises silicon structural layer, oxide layer and silicon substrate successively; By photoetching process and silicon etching process, silicon structural layer is graphically formed silicon lead-in wire successively, thus obtain silicon cover plate substrate; Grow insulating barrier at described silicon cover plate substrate surface by chemical vapor deposition, the top covering oxide layer and silicon lead-in wire of insulating barrier conformal and sidewall, thus silicon lead-in wire is wrapped in dielectric completely; The silicon cover plate substrate that grown insulating barrier is carried out high annealing in a nitrogen environment, border between the densified simultaneous oxidation layer of insulating barrier and insulating barrier is disappeared under the effect of counterdiffusion, by CMP process, planarization is carried out to surface of insulating layer, finally form insulating medium layer; On insulating medium layer, contact solder joint through hole and pressure welding electrode through hole is made by photoetching and follow-up etching or etching process; Growing mixed metal level on the silicon cover plate substrate contacting solder joint through hole and pressure welding electrode through hole is being defined by the method for magnetron sputtering or electron beam evaporation; Then carry out complex metal layer graphical after form weldering point contact electrode, pressure welding electrode and Vacuum Package solder ring respectively, finally prepared silicon cover plate.The process substrates of silicon cover plate is monocrystalline silicon disk, and the silicon substrate of silicon cover plate is single crystal silicon material, and silicon lead-in wire is single crystal silicon material.
Described composite material is made up of Ti, Pt, Au successively.
Described composite material is made up of Cr, Au successively.
Described insulating barrier is the composite insulation layer of SiO2, Si3N4 or SiO2 and Si3N4.
Described high temperature anneal temperature is 1000-1400 DEG C.
Described eutectic bonding pressure limit controls between 1000 newton-8000 newton, and eutectic bonding temperature controls between 360 DEG C-400 DEG C.
MEMS is gyroscope, accelerometer, resonator, wave filter, RF switch, pressure gauge or infrared focal plane device.
A kind of MEMS total silicon Vacuum Package device, comprise silicon cover plate and MEMS, described MEMS comprises device substrate, MEMS structure, silicon anchor point, silicon sealing ring and SiO2 insulator; The upper surface of MEMS structure, silicon anchor point, silicon sealing ring is in the same plane, and device substrate and silicon anchor point, silicon sealing ring are kept apart by SiO2 insulator; Silicon anchor point is positioned at silicon sealing ring, and MEMS structure is positioned at inside silicon anchor point; It is characterized in that, described silicon cover plate comprises silicon substrate, silicon lead-in wire, insulating medium layer, weldering point contact electrode, pressure welding electrode and Vacuum Package solder ring, insulating medium layer is positioned at above silicon substrate, silicon lead-in wire is embedded in insulating medium layer inside, weldering point contact electrode is by contact solder joint through hole and silicon wire contacts, pressure welding electrode is by pressure welding electrode through hole and silicon wire contacts, and Vacuum Package solder ring is positioned at outside weldering point contact electrode; Vacuum Package solder ring is contained in the groove of silicon sealing ring, and is fixedly connected with silicon sealing ring, thus forms vacuum seal cavity, makes described MEMS structure sealing structure in described vacuum seal cavity; Weldering point contact electrode is contained in the groove of silicon anchor point, and is fixedly connected with silicon anchor point, thus formation machinery is connected with electricity; The structural electric signal transmission of MEMS on corresponding silicon anchor point, then transfer to weldering point contact electrode on and by silicon lead-in wire and pressure welding electrode complete the signal of telecommunication extraction; Pressure welding electrode is positioned at MEMS outside.
The present invention compared with prior art, has following technique effect:
Vacuum Package scheme of the present invention adopts plane electrode lead-out mode, therefore only needs to arrange single Vacuum Package solder ring in device periphery, namely achieves the vacuum seal of device; Then without the need to arranging solder ring (chip area of general pressure welding surrounding them sealing solder ring consumption is 6-10 times of the area of pressure welding electrode own) around extraction electrode, thus greatly save the chip area of MEMS, be the preferred version of high-density packages.
The present invention adopts the signal of telecommunication lead-out mode of plane electrode only to have introducing parasitic capacitance at silicon lead-in wire and bonding region overlapping part, and the parasitic capacitance that this overlapping region is introduced generally is only the 1/10 even lower of TSV technology scheme introducing parasitic capacitance.
The present invention adopts silicon to go between as interconnecting pins, therefore overall package technique has higher process compatible temperature, thus the higher-quality insulating medium layer of more high density can be prepared on lead-in wire, thus improve processed finished products rate and the long term reliability of device.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and specific embodiments, the present invention is described in further detail:
Fig. 1-Fig. 6 is schematic diagram corresponding to silicon cover plate different processing technology step;
Fig. 7 is the plan view of silicon cover plate;
Fig. 8 is the sectional view of MEMS;
Fig. 9 is the plan view of MEMS;
Figure 10 is the structural representation of the MEMS total silicon Vacuum Package device adopting the present invention to make.
Specific implementation method
MEMS wafer-grade vacuum encapsulation method of the present invention comprises the steps:
One, silicon cover plate is prepared
(1) form the process substrates of silicon cover plate, as shown in Figure 1, the process substrates of silicon cover plate comprises silicon structural layer 1, oxide layer 2 and silicon substrate 3 successively.The process substrates of this silicon cover plate is silicon wafer, can be the monocrystalline silicon disk of low-resistivity, also can by being obtained by LPCVD technique growing polycrystalline silicon on monocrystalline silicon sheet surface, and its doping type can be N-shaped or p-type; The size of silicon wafer can be all sizes such as 3 inches-12 inches.Described monocrystalline silicon disk can be SOI (SiliconOnInsulator) type silicon chip.SOI sheet itself has three-decker, comprise monocrystalline substrate, oxide layer, single-crystal silicon device layer, therefore possessing same function with polysilicon epitaxial sheet, and directly adopting SOI to have the simple advantage of operation as silicon cover plate process substrates, therefore adopting SOI monocrystalline silicon disk to be preferred version.The silicon substrate of SOI sheet and its doping type of device layer can be N-shaped or p-type, and the size of silicon wafer can be 3 inches-12 inches.For ensureing that silicon interconnecting pins has lower resistance value and don't causes the excessive fluctuating of silicon cover plate substrate surface, the preferred thickness of SOI sheet device layer and epitaxial polysilicon layer is 200-500nm; For ensureing that insulating properties does not introduce again excessive material mismatch stress, oxidated layer thickness is preferably 1-3 μm; For ensureing that enough structural strengths do not cause again chip blocked up, Si-Substrate Thickness is preferably 250-500 μm.
(2) by photoetching process and silicon etching process, graphical for silicon structural layer 1 silicon formed as shown in Figure 2 is gone between 4 successively, thus obtain silicon cover plate substrate.In etching process, need the region that is etched of silicon structural layer 1 to etch completely totally to the oxide layer 2 exposing below.Above-mentioned silicon etching process can be that dry etch process is as reactive ion etching (RIE), inductively coupled plasma etching (ICP); Also can by making SiO
2anisotropic wet corrosion technique is adopted, as potassium hydroxide (KOH) solution corrosion, TMAH (TMAH) solution corrosion under the prerequisite of hard mask.The material of described silicon lead-in wire 4 can be that doped monocrystalline silicon, polysilicon etc. can the conductive materials of withstand high temperatures.
(3) as shown in Figure 3, at silicon cover plate substrate surface by the method growth insulating barrier 5 by chemical vapor depositions such as low-pressure chemical vapor phase deposition (LPCVD) or plasma enhanced CVD PECVD, insulating barrier 5 conformal cover above oxide layer 2 and the top of silicon lead-in wire 4 and sidewall, thus silicon lead-in wire 4 to be wrapped in dielectric completely; Described insulating barrier 5 can be silica or silicon nitride or both composite beds etc.
(4) after LPCVD technique, silicon cover plate substrate is carried out 1000-1400 DEG C of high annealing in a nitrogen environment, border between the densified simultaneous oxidation layer 2 of insulating barrier 5 and insulating barrier 5 is disappeared under the effect of counterdiffusion, by chemically mechanical polishing (CMP) technique, planarization is carried out to insulating barrier 5 surface, the insulating medium layer 6 that final formation is fine and close, homogeneous, smooth, as shown in Figure 4, thus be convenient to follow-up gold silicon eutectic bonding.And silicon materials itself have the high melting temperature of 1410 DEG C, the silicon chip therefore after interconnecting pins machines can prepare high-quality insulating medium layer by LPCVD (low-pressure chemical vapor phase deposition) and high-temperature annealing process.The insulating medium layer prepared by above-mentioned technique has very high compactness and electrical insulating property, has vital meaning to the yield rate and Long-Time Service reliability improving total silicon Vacuum Package MEMS.Described high temperature anneal temperature need lower than the melting temperature 1410 DEG C of silicon, and in the case for ensureing that SiO2 molecule or Si3N4 molecule have enough migration energy, high annealing is preferably 1200 DEG C.
(5) on insulating medium layer 6, contact solder joint through hole 7 and pressure welding electrode through hole 8 is made by photoetching and subsequent etching or etching process, as shown in Figure 5.Described contact solder joint through hole 7, pressure welding electrode through hole 8 are positioned at above silicon lead-in wire 4, and pressure welding electrode through hole 8 is positioned at the outside of contact solder joint through hole 7.
(6) by method growing mixed metal level on silicon cover plate substrate of magnetron sputtering or electron beam evaporation, preferred composition metal layered scheme, for be followed successively by Ti, Pt, Au from bottom to up, also can to adopt and be followed successively by Cr, Au metal level from bottom to up.The process costs considered and the tolerance degree of particle contamination, wherein the thickness of Au layer preferably controls between 500nm-2000nm, under the prerequisite taking into account cost and reliability, Ti metal level and Pt metal layer thickness preferably control between 50-100nm, and Cr metal layer thickness preferably controls between 100nm-150nm.Then carry out complex metal layer and graphically form weldering point contact electrode 9, pressure welding electrode 10, Vacuum Package solder ring 11 as shown in Figure 6 afterwards, finally prepare silicon cover plate 100.Weldering point contact electrode 9 to be positioned at above contact solder joint through hole 7 and to be gone between by contact solder joint through hole 7 and silicon and 4 to contact, pressure welding electrode 10 to be positioned at above pressure welding electrode through hole 8 and to be gone between by pressure welding electrode through hole 8 and silicon and 4 to contact, and Vacuum Package solder ring 11 is positioned at outside weldering point contact electrode 9.The difference of material selected by complex metal layer, this complex metal layer graphically can adopt photoetching/etch pattern scheme, also can adopt the process program of photoetching/ultrasonic stripping.Au metal level is as Au-Si eutectic reaction thing, and Ti/Cr metal level is adhesion layer, is sticked on insulating medium layer by complex metal layer, and Pt metal level is the diffusion impervious layer of upper and lower double layer of metal.
Two, MEMS is formed
Fig. 8 is a kind of MEMS 200 structural representation for wafer-level vacuum package.Device comprises device substrate 23, MEMS structure 20, silicon anchor point 21, silicon sealing ring 22 and SiO
2insulator 24.Device substrate 23 is positioned at topmost, and the upper surface of MEMS structure 20, silicon anchor point 21, silicon sealing ring 22 is in the same plane, SiO
2device substrate 23 is kept apart with silicon anchor point 21, silicon sealing ring 22 by insulator 24.Silicon sealing ring 22 is positioned at outermost, and silicon anchor point 21 is positioned at inside silicon sealing ring 22, and MEMS structure 20 is positioned at inside silicon anchor point 21; Fig. 9 is the plan view of MEMS 200.Form MEMS can exchange with the step preparing silicon cover plate.This MEMS can be gyroscope, accelerometer, resonator, wave filter, RF switch, pressure gauge, infrared focal plane device etc., is mainly applicable to the MEMS obtained by dry process.
Three, silicon cover plate 100 and MEMS 200 are carried out eutectic bonding in vacuum pressure bonder and complete wafer-level vacuum package, obtain total silicon vacuum MEMS.
As shown in Figure 10, Au-Si eutectic reaction is there is in the Vacuum Package solder ring 11 on silicon cover plate 100 and the silicon sealing ring 22 in MEMS 200 under the effect of pressure and temperature, wherein bonding pressure scope preferably controls between 1000 newton-8000 newton, and bonding temperature preferably controls between 360 DEG C-400 DEG C.Silicon cover plate 100 and MEMS 200 bond together by the eutectic product that reaction generates thickness, form vacuum seal cavity 25 as shown in Figure 10, by MEMS structure 20 sealing structure wherein.Silicon anchor point 21 in bonding process in MEMS 200, and there is Au-Si eutectic reaction equally in the weldering point contact electrode 9 on silicon cover plate 100, forms machinery and be connected with electricity.Electric signal transmission in MEMS structure 20 on corresponding silicon anchor point 21, then transfer to contact electrode 9 on and by imbed in insulating medium layer 6 silicon lead-in wire 4 and pressure welding electrode 10 complete the signal of telecommunication draw.Described silicon lead-in wire 4 is that the electricity for encapsulating cavity inner structure and pressure welding electrode is interconnected.It is outside that pressure welding electrode 10 is positioned at MEMS 200.Wherein Vacuum Package solder ring 11 is contained in the groove of silicon sealing ring 22, and weldering point contact electrode 9 is contained in the groove of silicon anchor point 21.Eutectic reaction can occur after Au and silicon are warmed up to eutectic temperature when compressing, the Au-Si eutectic product that reaction generates thickness realizes hermetically sealed as relying on the solder ring of sealing while the two-layer disk of solder attach to MEMS.
After completing Wafer level bonding, cutting-up is carried out to disk and be separated formation individual devices with chip.Because MEMS unit each on disk in cutting-up process achieves sealing, thus reduce the MEMS mechanical failure and pollution failure that cause in scribing sliver process.
For meeting the encapsulated vacuum degree demand of different components, the interior pressure of its cavity of method for packing of the present invention can control 1 × 10
-5in the scope of Pa-500Pa.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (10)
1. a full silicidation wafer-grade vacuum encapsulation method for MEMS, is characterized in that, comprise the steps:
Prepare silicon cover plate (100), described silicon cover plate comprises silicon substrate (3), silicon lead-in wire (4), insulating medium layer (6), weldering point contact electrode (9), pressure welding electrode (10) and Vacuum Package solder ring (11), insulating medium layer (6) is positioned at silicon substrate (3) top, it is inner that silicon lead-in wire (4) is positioned at insulating medium layer (6), weldering point contact electrode (9) by contact solder joint through hole (7) go between with silicon (4) contact, pressure welding electrode (10) by pressure welding electrode through hole (8) to go between with silicon (4) contact, Vacuum Package solder ring (11) is positioned at weldering point contact electrode (9) outside,
Preparation MEMS (200); Described MEMS comprises device substrate (23), MEMS structure (20), silicon anchor point (21), silicon sealing ring (22) and SiO
2insulator (24);
Silicon cover plate (100) and MEMS (200) are carried out eutectic bonding in vacuum pressure bonder and completes full silicidation wafer-level vacuum package, there is eutectic reaction in described Vacuum Package solder ring (11) and silicon sealing ring (22), thus silicon cover plate (100) and MEMS (200) are bonded together, form vacuum seal cavity (25), described MEMS structure (20) sealing structure is in described vacuum seal cavity (25); There is eutectic reaction in described weldering point contact electrode (9) and silicon anchor point (21), forms machinery and be connected with electricity; Electric signal transmission in MEMS structure (20) is on corresponding silicon anchor point (21), transfer to weldering point contact electrode (9) upper and complete the signal of telecommunication by silicon lead-in wire (4) and pressure welding electrode (10) and draw, pressure welding electrode (10) is positioned at MEMS (200) outside.
2. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 1, is characterized in that, the method preparing silicon cover plate is as follows:
Form the process substrates of silicon cover plate, the process substrates of silicon cover plate comprises silicon structural layer (1), oxide layer (2) and silicon substrate (3) successively;
Silicon structural layer (1) is graphically formed silicon lead-in wire (4) by photoetching process and silicon etching process successively, thus obtain silicon cover plate substrate;
Insulating barrier (5) is grown by chemical vapor deposition at described silicon cover plate substrate surface, the top covering oxide layer (2) top and silicon lead-in wire (4) of insulating barrier 5 conformal and sidewall, thus silicon lead-in wire (4) is wrapped in dielectric completely;
The silicon cover plate substrate that grown insulating barrier (5) is carried out high annealing in a nitrogen environment, border between the densified simultaneous oxidation layer (2) of insulating barrier (5) and insulating barrier (5) is disappeared under the effect of counterdiffusion, by CMP process, planarization is carried out to insulating barrier (5) surface, finally form insulating medium layer (6);
Contact solder joint through hole (7) and pressure welding electrode through hole (8) is made insulating medium layer (6) is upper by photoetching and follow-up etching or etching process;
Growing mixed metal level on the silicon cover plate substrate contacting solder joint through hole (7) and pressure welding electrode through hole (8) is being defined by the method for magnetron sputtering or electron beam evaporation; Then carry out complex metal layer graphical after form weldering point contact electrode (9), pressure welding electrode (10) and Vacuum Package solder ring (11) respectively, finally prepared silicon cover plate (100).
3. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 2, it is characterized in that, the process substrates of silicon cover plate is monocrystalline silicon disk, and the silicon substrate (3) of silicon cover plate is single crystal silicon material, and silicon lead-in wire (4) is single crystal silicon material.
4. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 2, is characterized in that, described composite material is made up of Ti, Pt, Au successively.
5. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 2, is characterized in that, described composite material is made up of Cr, Au successively.
6. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 2, is characterized in that, described insulating barrier is the composite insulation layer of SiO2, Si3N4 or SiO2 and Si3N4.
7. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 2, is characterized in that, described high temperature anneal temperature is 1000-1400 DEG C.
8. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 1, is characterized in that, described eutectic bonding pressure limit controls between 1000 newton-8000 newton, and eutectic bonding temperature controls between 360 DEG C-400 DEG C.
9. the full silicidation wafer-grade vacuum encapsulation method of a kind of MEMS according to claim 1, is characterized in that, MEMS is gyroscope, accelerometer, resonator, wave filter, RF switch, pressure gauge or infrared focal plane device.
10. a MEMS total silicon Vacuum Package device, comprise silicon cover plate (100) and MEMS (200), described MEMS comprises device substrate (23), MEMS structure (20), silicon anchor point (21), silicon sealing ring (22) and SiO
2insulator (24), the upper surface of MEMS structure (20), silicon anchor point (21), silicon sealing ring (22) is in the same plane, SiO
2device substrate (23) and silicon anchor point (21), silicon sealing ring (22) are kept apart by insulator (24), silicon anchor point (21) is positioned at silicon sealing ring (22), and MEMS structure (20) is positioned at silicon anchor point (21) inner side, it is characterized in that, described silicon cover plate comprises silicon substrate (3), silicon lead-in wire (4), insulating medium layer (6), weldering point contact electrode (9), pressure welding electrode (10) and Vacuum Package solder ring (11), insulating medium layer (6) is positioned at silicon substrate (3) top, it is inner that silicon lead-in wire (4) is embedded in insulating medium layer (6), weldering point contact electrode (9) by contact solder joint through hole (7) go between with silicon (4) contact, pressure welding electrode (10) by pressure welding electrode through hole (8) to go between with silicon (4) contact, Vacuum Package solder ring (11) is positioned at weldering point contact electrode (9) outside, Vacuum Package solder ring (11) is contained in the groove of silicon sealing ring (22), and be fixedly connected with silicon sealing ring (22), thus form vacuum seal cavity (25), make described MEMS structure (20) sealing structure in described vacuum seal cavity (25), weldering point contact electrode (9) is contained in the groove of silicon anchor point (21), and is fixedly connected with silicon anchor point (21), thus formation machinery is connected with electricity, electric signal transmission in MEMS structure (20) is on corresponding silicon anchor point (21), then it is upper and complete signal of telecommunication extraction by silicon lead-in wire (4) and pressure welding electrode (10) to transfer to weldering point contact electrode (9), it is outside that pressure welding electrode (10) is positioned at MEMS (200).
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