CN105226962A - Intelligent power module and air conditioner - Google Patents
Intelligent power module and air conditioner Download PDFInfo
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Abstract
The invention provides a kind of Intelligent Power Module and air conditioner, Intelligent Power Module comprises: brachium pontis signal input part and temperature detection end under brachium pontis signal input part, three-phase on three-phase; HVIC pipe is provided with the terminals being connected to brachium pontis signal input part under brachium pontis signal input part and three-phase on three-phase respectively, and corresponding to the first port of temperature detection end, the first port can export corresponding magnitude of voltage according to the change in resistance of thermistor in Intelligent Power Module; The input of self-checking circuit is connected to brachium pontis signal input part in U phase, the output of self-checking circuit is connected to the U phase higher-pressure region signal output part of HVIC pipe, the input/output terminal of self-checking circuit is connected to described first port, self-checking circuit is used for the signal of brachium pontis signal input part in U phase to be sent to U phase higher-pressure region signal output part, and when HVIC manages initial work, thermistor is detected, to compensate the resistance of thermistor when thermistor exception being detected.
Description
Technical field
The present invention relates to Intelligent Power Module technical field, in particular to a kind of Intelligent Power Module and a kind of air conditioner.
Background technology
Intelligent Power Module (IntelligentPowerModule, be called for short IPM) be a kind of analog line driver that power electronics discrete device and integrated circuit technique are integrated, Intelligent Power Module comprises device for power switching and high-voltage driving circuit, and with overvoltage, overcurrent and the failure detector circuit such as overheated.The logic input terminal of Intelligent Power Module receives the control signal of master controller, and output drives compressor or subsequent conditioning circuit work, sends the system status signal detected back to master controller simultaneously.Relative to traditional discrete scheme; Intelligent Power Module has the advantages such as high integration, high reliability, self-inspection and protective circuit; being particularly suitable for the frequency converter of drive motors and various inverter, is the desired power level electronic device of frequency control, metallurgical machinery, electric traction, servo-drive, frequency-conversion domestic electric appliances.
The structural representation of existing Intelligent power module circuit as shown in Figure 1, TTRIP port is as temperature detection end, be generally used for by NTC (NegativeTemperatureCoefficient, negative temperature coefficient) change of thermistor resistance exports different voltage, subsequent conditioning circuit controls Intelligent Power Module by the change of the change or Intelligent Power Module temperature that detect this magnitude of voltage and carries out work, particularly, when the voltage detected is lower than a certain particular value, namely when temperature is higher than a certain particular value, control Intelligent Power Module quits work and Intelligent Power Module is lowered the temperature, Intelligent Power Module is avoided to be operated in the too high state of temperature and thermal breakdown occurs.
But, along with the development of semiconductor technology, IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor) and HVIC (HighVoltageintegratedcircuit, high voltage integrated circuit) useful life improve constantly, generally have the useful life of 5 ~ 8 years, and NTC at high temperature flows continuously through electric current, its temperature variation curve starts deterioration in use after 3 ~ 5 years.Specifically as shown in Figure 2; NTC is in later stage of life; resistance under normal temperature does not have significant change; but along with the increase of temperature, under high temperature, resistance obviously declines, and peripheral circuit generally detects fixing resistance Rth; once resistance value is lower than Rth; i.e. trigger protection, therefore along with the deterioration of NTC, the temperature of trigger protection reduces to T1 from T2.
In general, Intelligent Power Module can be operated in the environment of 125 DEG C, therefore T2 temperature is generally designed to more than 100 DEG C, but along with the deterioration of NTC thermistor, temperature T1 when resistance drops to Rth is less than T2, once T1 is lower than 80 DEG C, module will be difficult to normal work, cause module to scrap, then make systemic breakdown.In the Material Cost of Intelligent Power Module, the price of thermistor is very low, how to avoid causing Intelligent Power Module to lose efficacy because of the deterioration of thermistor, is current Intelligent Power Module problem demanding prompt solution.
Summary of the invention
The present invention is intended at least to solve one of technical problem existed in prior art or correlation technique.
For this reason, one object of the present invention is to propose a kind of new Intelligent Power Module, can when the initial work of Intelligent Power Module, thermistor is detected, to compensate the resistance of described thermistor when described thermistor exception being detected, significantly extend the life cycle of Intelligent Power Module, improve the useful life of Intelligent Power Module.
For achieving the above object, embodiment according to a first aspect of the invention, proposes a kind of Intelligent Power Module, comprising: brachium pontis signal input part and temperature detection end under brachium pontis signal input part, three-phase on three-phase, HVIC manages, described HVIC pipe is provided with the terminals being connected to brachium pontis signal input part under brachium pontis signal input part and described three-phase on described three-phase respectively, and correspond to the first port of described temperature detection end, described first port is connected with described temperature detection end by connecting line, and described first port can export corresponding magnitude of voltage according to the change in resistance of thermistor in described Intelligent Power Module, self-checking circuit, the low-pressure area power supply positive pole of described self-checking circuit and negative pole are connected to low-pressure area power supply anode and the negative terminal of described Intelligent Power Module respectively, the higher-pressure region power supply positive pole of described self-checking circuit and negative pole are connected to U phase higher-pressure region power supply anode and the negative terminal of described Intelligent Power Module respectively, brachium pontis signal input part in the U phase that the input of described self-checking circuit is connected to described Intelligent Power Module, the output of described self-checking circuit is connected to the U phase higher-pressure region signal output part of described HVIC pipe, the input/output terminal of described self-checking circuit is connected to described first port, described self-checking circuit is used for the signal of brachium pontis signal input part in described U phase to be sent to described U phase higher-pressure region signal output part, and when described HVIC manages initial work, described thermistor is detected, to compensate the resistance of described thermistor when described thermistor exception being detected.
Intelligent Power Module according to an embodiment of the invention, by arranging self-checking circuit when HVIC manages initial work, thermistor is detected, to compensate the resistance of described thermistor when described thermistor exception being detected, significantly can extend the life cycle of Intelligent Power Module, improve the useful life of Intelligent Power Module, the application for the high-end applications occasion of Intelligent Power Module plays an important role.
Intelligent Power Module according to the abovementioned embodiments of the present invention, can also have following technical characteristic:
According to one embodiment of present invention, described self-checking circuit comprises:
Input circuit, the power supply positive pole of described input circuit and negative pole are respectively as the low-pressure area power supply positive pole of described self-checking circuit and negative pole, the input of described input circuit is as the input of described self-checking circuit, the output of described input circuit is connected to the input of the first not gate, the output of described first not gate is connected to the input of the second not gate, the output of described second not gate is connected to the first input end of the first NAND gate, and described input circuit is used for carrying out noise filtering process to the signal of input;
3rd not gate, the input of described 3rd not gate is connected to the input of described first not gate, the output of described 3rd not gate is connected to the input of the first resistance, the output of described first resistance is connected to the input of the 4th not gate, the output of described 4th not gate is connected to the input of the 5th not gate, the output of described 5th not gate is connected to the second input of described first NAND gate, the output of described first NAND gate is connected to the input of the 6th not gate, the output of described 6th not gate is connected to the grid of the first DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described first DMOS pipe is connected with source electrode,
First electric capacity, the first end of described first electric capacity is connected to the input of described 4th not gate, and the second end of described first electric capacity is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module;
7th not gate, the input of described 7th not gate is connected to the output of described input circuit, and the output of described 7th not gate is connected to the first input end of the second NAND gate;
8th not gate, the input of described 8th not gate is connected to the output of described input circuit, the output of described 8th not gate is connected to the first end of the second resistance, second end of described second resistance is connected to the input of the 9th not gate, the output of described 9th not gate is connected to the second input of described second NAND gate, the output of described second NAND gate is connected to the input of the tenth not gate, the output of described tenth not gate is connected to the grid of the second DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described second DMOS pipe is connected with source electrode,
Second electric capacity, the first end of described second electric capacity is connected to the input of described 9th not gate, and the second end of described second electric capacity is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module;
First rest-set flip-flop, the S end of described first rest-set flip-flop is connected to the output of described tenth not gate, the R end of described first rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described first rest-set flip-flop is connected to the stiff end of the first analog switch, the selecting side of described first analog switch is connected to the input of the 11 not gate, the output of described 11 not gate is connected to the input of the 12 not gate, the output of described 12 not gate is connected to the input of the 13 not gate, the output of described 13 not gate is connected to the input of the 14 not gate, the output of described 14 not gate is connected to the S end of the second rest-set flip-flop, the R end of described second rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described second rest-set flip-flop is connected to the control end of described first analog switch,
Voltage comparator, the positive input terminal of described voltage comparator is connected to the selecting side of the second analog switch, the control end of described second analog switch is connected to the output of described 14 not gate, the stiff end of described second analog switch is connected to the anode of the first voltage source, the negative terminal of described first voltage source is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the negative input end of described voltage comparator is connected to the first end of described thermistor, second end of described thermistor is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the output of described voltage comparator is connected to the S end of the 3rd rest-set flip-flop, the R end of described 3rd rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described 3rd rest-set flip-flop is connected to the control end of the 3rd analog switch, the stiff end of described 3rd analog switch is connected to the first end of described thermistor, first selecting side of described 3rd analog switch is as described first port, second selecting side of described 3rd analog switch is connected to the first end of the first resistance, second end of described first resistance is connected to the first selecting side of described 3rd analog switch,
4th analog switch, the control end of described 4th analog switch is connected to the input of described 13 not gate, the stiff end of described 4th analog switch is connected to the negative input end of described voltage comparator, the selecting side of described 4th analog switch is connected to the anode of the second voltage source, and the negative terminal of described second voltage source is connected to the power supply positive pole of described input circuit;
Output circuit, the power supply positive pole of described output circuit and negative pole are respectively as the higher-pressure region power supply positive pole of described self-checking circuit and negative pole, the first input end of described output circuit is connected to the drain electrode of described first DMOS pipe, second input of described output circuit is connected to the drain electrode of described second DMOS pipe, the output of described output circuit is as the output of described self-checking circuit, that described output circuit is used for that to be treated to the U phase higher-pressure region power supply negative terminal of described Intelligent Power Module by the pulse signal of described output circuit first input end and the pulse signal of the second input be benchmark and consistent with the input signal phase place of brachium pontis signal input part in the U phase of described Intelligent Power Module continuous signal,
5th analog switch, the stiff end of described 5th analog switch is connected to the output of described input circuit, the control end of described 5th analog switch is connected to the input of described 11 not gate, the selecting side of described 5th analog switch is connected to the grid of the 3rd DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described 3rd DMOS pipe is connected with source electrode, the drain electrode of described 3rd DMOS pipe is connected to the first end of the second resistance, and the second end of described second resistance is connected to the power supply positive pole of described output circuit.
According to one embodiment of present invention, also comprise boostrap circuit, described boostrap circuit comprises: the first bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described first bootstrap diode is connected to described U phase higher-pressure region power supply anode; Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described Intelligent Power Module; 3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described Intelligent Power Module.
According to one embodiment of present invention, also comprise: bridge arm circuit on three-phase, in each phase on described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase high-voltage district of described HVIC pipe; Bridge arm circuit under three-phase, under each phase under described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase low-voltage district of described HVIC pipe.
Wherein, on three-phase, bridge arm circuit comprises: bridge arm circuit in bridge arm circuit, W phase in bridge arm circuit, V phase in U phase; Under three-phase, bridge arm circuit comprises: the lower bridge arm circuit of the lower bridge arm circuit of U phase, V phase, the lower bridge arm circuit of W phase.
According to one embodiment of present invention, in each phase described, bridge arm circuit comprises: the first power switch pipe and the first diode, the anode of described first diode is connected to the emitter of described first power switch pipe, the negative electrode of described first diode is connected to the collector electrode of described first power switch pipe, the collector electrode of described first power switch pipe is connected to the high voltage input of described Intelligent Power Module, the base stage of described first power switch pipe is as the input of bridge arm circuit in each phase described, the emitter of described first power switch pipe is connected to the higher-pressure region power supply negative terminal of the corresponding phase of described Intelligent Power Module.
Wherein, the first power switch pipe can be IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor).
According to one embodiment of present invention, under each phase described, bridge arm circuit comprises: the second power switch pipe and the second diode, the anode of described second diode is connected to the emitter of described second power switch pipe, the negative electrode of described second diode is connected to the collector electrode of described second power switch pipe, the collector electrode of described second power switch pipe is connected to the anode of described first diode in corresponding upper bridge arm circuit, and the base stage of described second power switch pipe is as the input of bridge arm circuit under each phase described.
Wherein, the second power switch pipe can be IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor).
According to one embodiment of present invention, the emitter of described second power switch pipe under each phase described in bridge arm circuit is as the low reference voltage end of the corresponding phase of described Intelligent Power Module.
According to one embodiment of present invention, the voltage of the high voltage input of described Intelligent Power Module is 300V.
According to one embodiment of present invention, filter capacitor is connected with between the higher-pressure region power supply anode of each phase and higher-pressure region power supply negative terminal in described HVIC pipe.
Embodiment according to a second aspect of the present invention, also proposed a kind of air conditioner, comprising: as the Intelligent Power Module described in above-mentioned any one embodiment.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 shows the structural representation of the Intelligent Power Module in correlation technique;
Fig. 2 shows the resistance variation with temperature relation schematic diagram of thermistor in later stage of life;
Fig. 3 shows the structural representation of Intelligent Power Module according to an embodiment of the invention;
Fig. 4 shows the internal structure schematic diagram of self-checking circuit according to an embodiment of the invention.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not by the restriction of following public specific embodiment.
Fig. 3 shows the structural representation of Intelligent Power Module according to an embodiment of the invention.
As shown in Figure 3, Intelligent Power Module according to an embodiment of the invention, comprising: HVIC pipe 1101 and self-checking circuit 1105.
Wherein, inner at HVIC pipe 1101:
HIN1 end connects the input of self-checking circuit 1105; TTRIP end connects the input/output terminal of self-checking circuit 1105; VCC end connects the low-pressure area power supply anode of self-checking circuit 1105; GND end connects the low-pressure area power supply negative terminal of self-checking circuit 1105; VB1 end connects the higher-pressure region power supply anode of self-checking circuit 1105; VS1 end connects the higher-pressure region power supply negative terminal of self-checking circuit 1105; The output of self-checking circuit 1105 is connected with HO1.
HVIC pipe 1101 inside also has boostrap circuit structure as follows:
VCC end is connected with the anode of bootstrap diode 1102, bootstrap diode 1103, bootstrap diode 1104; The negative electrode of bootstrap diode 1102 is connected with the VB1 of HVIC pipe 1101; The negative electrode of bootstrap diode 1103 is connected with the VB2 of HVIC pipe 1101; The negative electrode of bootstrap diode 1104 is connected with the VB3 of HVIC pipe 1101.
HVIC pipe 1101 HIN1 end for Intelligent Power Module 1100 U phase on brachium pontis signal input part UHIN; HVIC pipe 1101 HIN2 end for Intelligent Power Module 1100 V phase on brachium pontis signal input part VHIN; HVIC pipe 1101 HIN3 end for Intelligent Power Module 1100 W phase on brachium pontis signal input part WHIN; The LIN1 end of HVIC pipe 1101 is the lower brachium pontis signal input part ULIN of U phase of Intelligent Power Module 1100; The LIN2 end of HVIC pipe 1101 is the lower brachium pontis signal input part VLIN of V phase of Intelligent Power Module 1100; The LIN3 end of HVIC pipe 1101 is the lower brachium pontis signal input part WLIN of W phase of Intelligent Power Module 1100; The ITRIP of HVIC pipe 1101 holds as the MTRIP of Intelligent Power Module 1100 holds; The GND of HVIC pipe 1101 holds the low-pressure area power supply negative terminal COM as Intelligent Power Module 1100.Wherein, Intelligent Power Module 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input receive the input signal of 0V or 5V.
The VB1 end of HVIC pipe 1101 connects one end of electric capacity 1131, and as the U phase higher-pressure region power supply anode UVB of Intelligent Power Module 1100; The HO1 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1121 in U phase; The VS1 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1121, FRD pipe 1111, the collector electrode of the lower brachium pontis IGBT pipe 1124 of U phase, the negative electrode of FRD pipe 1114, the other end of electric capacity 1131, and as the U phase higher-pressure region power supply negative terminal UVS of Intelligent Power Module 1100.
The VB2 end of HVIC pipe 1101 connects one end of electric capacity 1132, and as the V phase higher-pressure region power supply anode VVB of Intelligent Power Module 1100; The HO2 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in V phase; The VS2 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1122, FRD pipe 1112, the collector electrode of the lower brachium pontis IGBT pipe 1125 of V phase, the negative electrode of FRD pipe 1115, the other end of electric capacity 1132, and as the V phase higher-pressure region power supply negative terminal VVS of Intelligent Power Module 1100.
The VB3 end of HVIC pipe 1101 connects one end of electric capacity 1133, as the W phase higher-pressure region power supply anode WVB of Intelligent Power Module 1100; The HO3 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in W phase; The VS3 end of HVIC pipe 1101 is connected with the anode of the emitter-base bandgap grading of IGBT pipe 1123, FRD pipe 1113, the collector electrode of the lower brachium pontis IGBT pipe 1126 of W phase, the negative electrode of FRD pipe 1116, the other end of electric capacity 1133, and as the W phase higher-pressure region power supply negative terminal WVS of Intelligent Power Module 1100.
The LO1 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1124; The LO2 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1125; The LO3 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1126; The emitter-base bandgap grading of IGBT pipe 1124 is connected with the anode of FRD pipe 1114, and as the U phase low reference voltage end UN of Intelligent Power Module 1100; The emitter-base bandgap grading of IGBT pipe 1125 is connected with the anode of FRD pipe 1115, and as the V phase low reference voltage end VN of Intelligent Power Module 1100; The emitter-base bandgap grading of IGBT pipe 1126 is connected with the anode of FRD pipe 1116, and as the W phase low reference voltage end WN of Intelligent Power Module 1100.
The collector electrode of the collector electrode of the collector electrode of IGBT pipe 1121, the negative electrode of FRD pipe 1111, IGBT pipe 1122, the negative electrode of FRD pipe 1112, IGBT pipe 1123, the negative electrode of FRD pipe 1113 are connected, and as the high voltage input P of Intelligent Power Module 1100, P generally meets 300V.
VDD is HVIC pipe 1101 power supply anode, and GND is the power supply negative terminal of HVIC pipe 1101; VDD-GND voltage is generally 15V; VB1 and VS1 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the output of U phase higher-pressure region; VB2 and VS2 is respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the output of V phase higher-pressure region; VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the output of W phase higher-pressure region; LO1, LO2, LO3 are respectively the output of U phase, V phase, W phase low-pressure area.
The effect of HVIC pipe 1101 is: the logic input signal of 0 of input HIN1, HIN2, HIN3 or 5V is passed to output HO1, HO2, HO3 respectively, the signal of LIN1, LIN2, LIN3 passes to output LO1, LO2, LO3 respectively, wherein HO1 be the logic output signal of VS1 or VS1+15V, the HO2 logic output signal that is VS2 or VS2+15V, the HO3 logic output signal that is VS3 or VS3+15V, LO1, LO2, LO3 are the logic output signals of 0 or 15V.
The effect of self-checking circuit 1105 is: when the 1101 initial work of HVIC pipe, except making the signal of HIN1 be sent to except HO1, also producing localized hyperthermia in self-checking circuit 1105 inside, self-inspection is carried out to temperature-sensitive device, when the value of temperature-sensitive device occurs abnormal, automatically compensate; After HVIC pipe 1101 normally work, make the signal of HIN1 be sent to HO1, the localized hyperthermia of self-checking circuit 1105 stops, and temperature-sensitive device is according to this precompensation or uncompensated operation.
Wherein, the particular circuit configurations schematic diagram of self-checking circuit 1105 as shown in Figure 4, is specially:
HIN1 connects the input of input circuit 2037; VCC connects the power supply anode of input circuit 2037; GND connects the power supply negative terminal of input circuit 2037; The stiff end of the input of the input of the output NAND gate 2014 of input circuit 2037, the input of not gate 2016, not gate 2023, the input of not gate 2024, analog switch 2002 is connected.
The input of the output termination not gate 2015 of not gate 2014, the output of not gate 2015 connects one of them input of NAND gate 2021; One end of the output connecting resistance 2020 of not gate 2016; One end of another termination capacitor 2019 of resistance 2020, the input of not gate 2017; The input of the output termination not gate 2018 of not gate 2017, another input of the output termination NAND gate 2021 of not gate 2018; Another termination GND of electric capacity 2019.
One of them input of the output termination NAND gate 2028 of not gate 2023; One end of the output connecting resistance 2027 of not gate 2024, one end of another termination capacitor 2026 of resistance 2027 and the input of not gate 2025; Another termination GND of electric capacity 2026; Another input of the output termination NAND gate 2028 of not gate 2025.
The input of the output termination not gate 2022 of NAND gate 2021, the grid of the output terminated high voltage DMOS pipe 2031 of not gate 2022; The substrate of high pressure DMOS pipe 2031 is connected with source electrode and meets GND; The drain electrode of high pressure DMOS pipe 2031 is connected with the first input end of output circuit 2032.
The input of the output termination not gate 2029 of NAND gate 2028, the grid of the output terminated high voltage DMOS pipe 2030 of not gate 2029 and the S end of rest-set flip-flop 2001; The substrate of high pressure DMOS pipe 2030 is connected with source electrode and meets GND; The drain electrode of high pressure DMOS pipe 2030 is connected with the second input of output circuit 2032.
The positive termination VB1 of power supply of output circuit 2032; The power supply negative terminal of output circuit 2032 meets VS1; The output termination HO1 of output circuit 2032.
The R termination GND of rest-set flip-flop 2001; The stiff end of the Q termination analog switch 2037 of rest-set flip-flop 2001, the control end of selection termination analog switch 2002 of analog switch 2037 and the input of not gate 2034; The grid of the selection terminated high voltage DMOS pipe 2003 of analog switch 2002, the substrate of high pressure DMOS pipe 2003 is connected with source electrode one end of GND, the drain electrode connecting resistance 2036 of high pressure DMOS pipe 2003, another termination VB1 of resistance 2036.
The input of the output termination not gate 2035 of not gate 2034, the input of output termination not gate 2011 of not gate 2035, the control end of analog switch 2013; The input of the output termination not gate 2012 of not gate 2011, the control end of the output termination analog switch 2007 of not gate 2012 and the S end of rest-set flip-flop 2038; The R termination GND of rest-set flip-flop 2038, the control end of the Q termination analog switch 2037 of rest-set flip-flop 2038.
The anode of the fixing termination voltage source 2005 of analog switch 2007, the negative terminal of voltage source 2005 meets GND; The anode input of the selection termination voltage comparator 2008 of analog switch 2007, one end of the negative input termination thermistor 2004 of voltage comparator 2008, the stiff end of analog switch 2009, the stiff end of analog switch 2013; The anode of the selection termination current source 2033 of analog switch 2013, the negative terminal of current source 2033 meets VCC.
The S end of the output termination rest-set flip-flop 2006 of voltage comparator 2008, the R termination GND of rest-set flip-flop 2006, the control end of the Q termination analog switch 2009 of rest-set flip-flop 2006; 0 of analog switch 2009 selects termination TTRIP, one end of 1 selecting side connecting resistance 2010 of analog switch 2009, another termination TTRIP of resistance 2010.
Operation principle and the key parameter value of the above embodiment of the present invention are below described:
The effect of input circuit 2037 is the noises filtering HIN1, and the logic voltage of 0 ~ 5V of input is boosted to the logic voltage of 0 ~ 15V.
When initially powering on, analog switch 2002 is closed, analog switch 2009 in 0 selecting side, analog switch 2007 is opened, analog switch 2013 is opened, analog switch 2037 closes.
Then come interim at first high level of HIN1: at the rising edge of HIN1, A point generation pulse; At the trailing edge of HIN1, B point generation pulse; The time of delay of the network that the width of above-mentioned two pulses is made up of resistance 2020, electric capacity 2019 respectively and the network that resistance 2027, electric capacity 2026 form determines, usually, this delay time can be designed to 200ns ~ 300ns and much smaller than the duration 1 μ s ~ number μ s of the high level of HIN1, thus can avoid the heating that high pressure DMOS pipe 2031 and high pressure DMOS pipe 2030 cause because service time is long.
But in the whole high level time of HIN1, high pressure DMOS pipe 2003 conducting always because of the closed of analog switch 2002, thus larger electric current is flow through in 1 μ s ~ number μ s, the size of this electric current is controlled by resistance 2036, usually, resistance 2036 is designed to k Ω rank, then flow through the electric current of high pressure DMOS pipe 2003 in tens of mA rank, and near high pressure DMOS pipe 2003, moment local pyrexia is to more than 80 DEG C.
Thermistor 2004 designs near high pressure DMOS pipe 2003 on circuit layout, and therefore, thermistor 2004 is also heated up instantaneously.
After the high level of HIN1 terminates, under the effect of the high level pulse of B point generation, the Q end of rest-set flip-flop 2001 produces high level makes analog switch 2002 disconnect, thus DMOS pipe 2003 stops heating; Through the time delay T1 of not gate 2034 and not gate 2035, high level signal passes to analog switch 2013 and closes, thus has electric current to flow through by the thermistor 2004 after heating, thus at the negative terminal coating-forming voltage of voltage comparator 2008; Again through the time delay T2 of not gate 2011 and not gate 2012, the closed anode making the voltage access voltage comparator 2008 of voltage source 2005 of analog switch 2007; At this, not gate 2034, not gate 2035, not gate 2011, not gate 2012 are designed to 2 times of technique permission minimum dimension, then time delay T1 and T2 produced is in the rank of 10ns, and in the time of 10ns, the temperature of thermistor 2004 thinks constant.
If when thermistor 2004 is not completely deteriorated, the resistance of 80 DEG C is greater than 10k Ω, and current source 2003 can be designed to 50 μ A ranks, and voltage source 2005 can be designed to 0.5V rank; If then thermistor 2004 is not completely deteriorated, voltage comparator 2008 output low level, makes one end of thermistor 2004 directly be connected with TTRIP; If thermistor 2004 is deteriorated, voltage comparator 2008 exports high level, and one end of thermistor 2004 is connected with one end of resistance 2010.Further, the high level that not gate 2012 exports makes the Q of rest-set flip-flop 2038 export high level, thus analog switch 2037 disconnects, and analog switch 2013 and analog switch 2007 also disconnect in succession again.At the later high level of HIN1, no longer high pressure DMOS pipe 2003 controlled, no longer analog switch 2009 controlled.
In sum, when thermistor 2004 is not completely deteriorated, the resistance of TTRIP monitoring thermistor 2004 carrys out the temperature of judge module; When thermistor 2004 deterioration, the resistance of TTRIP monitoring thermistor 2004 and resistance 2010 carrys out the temperature of judge module.By resistance 2010 for temperature coefficient is designed within 1%, resistance can be designed to 3 ~ 5k Ω according to practical application and supplement the thermistor after deterioration, extends the life-span of Intelligent Power Module.
From the technical scheme of above-described embodiment, Intelligent Power Module and the existing Intelligent Power Module of the present invention's proposition are completely compatible, can directly replace with existing Intelligent Power Module, and compensated by the state of the temperature-sensitive device of automatic decision Intelligent Power Module, significantly extend the life cycle of Intelligent Power Module, the application for the high-end applications occasion of Intelligent Power Module plays an important role.
More than be described with reference to the accompanying drawings technical scheme of the present invention, the present invention proposes a kind of new Intelligent Power Module, can when the initial work of Intelligent Power Module, thermistor is detected, to compensate the resistance of described thermistor when described thermistor exception being detected, significantly extend the life cycle of Intelligent Power Module, improve the useful life of Intelligent Power Module.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. an Intelligent Power Module, is characterized in that, comprising:
Brachium pontis signal input part and temperature detection end under brachium pontis signal input part, three-phase on three-phase;
HVIC manages, described HVIC pipe is provided with the terminals being connected to brachium pontis signal input part under brachium pontis signal input part and described three-phase on described three-phase respectively, and correspond to the first port of described temperature detection end, described first port is connected with described temperature detection end by connecting line, and described first port can export corresponding magnitude of voltage according to the change in resistance of thermistor in described Intelligent Power Module;
Self-checking circuit, the low-pressure area power supply positive pole of described self-checking circuit and negative pole are connected to low-pressure area power supply anode and the negative terminal of described Intelligent Power Module respectively, the higher-pressure region power supply positive pole of described self-checking circuit and negative pole are connected to U phase higher-pressure region power supply anode and the negative terminal of described Intelligent Power Module respectively, brachium pontis signal input part in the U phase that the input of described self-checking circuit is connected to described Intelligent Power Module, the output of described self-checking circuit is connected to the U phase higher-pressure region signal output part of described HVIC pipe, the input/output terminal of described self-checking circuit is connected to described first port, described self-checking circuit is used for the signal of brachium pontis signal input part in described U phase to be sent to described U phase higher-pressure region signal output part, and when described HVIC manages initial work, described thermistor is detected, to compensate the resistance of described thermistor when described thermistor exception being detected.
2. Intelligent Power Module according to claim 1, is characterized in that, described self-checking circuit comprises:
Input circuit, the power supply positive pole of described input circuit and negative pole are respectively as the low-pressure area power supply positive pole of described self-checking circuit and negative pole, the input of described input circuit is as the input of described self-checking circuit, the output of described input circuit is connected to the input of the first not gate, the output of described first not gate is connected to the input of the second not gate, the output of described second not gate is connected to the first input end of the first NAND gate, and described input circuit is used for carrying out noise filtering process to the signal of input;
3rd not gate, the input of described 3rd not gate is connected to the input of described first not gate, the output of described 3rd not gate is connected to the input of the first resistance, the output of described first resistance is connected to the input of the 4th not gate, the output of described 4th not gate is connected to the input of the 5th not gate, the output of described 5th not gate is connected to the second input of described first NAND gate, the output of described first NAND gate is connected to the input of the 6th not gate, the output of described 6th not gate is connected to the grid of the first DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described first DMOS pipe is connected with source electrode,
First electric capacity, the first end of described first electric capacity is connected to the input of described 4th not gate, and the second end of described first electric capacity is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module;
7th not gate, the input of described 7th not gate is connected to the output of described input circuit, and the output of described 7th not gate is connected to the first input end of the second NAND gate;
8th not gate, the input of described 8th not gate is connected to the output of described input circuit, the output of described 8th not gate is connected to the first end of the second resistance, second end of described second resistance is connected to the input of the 9th not gate, the output of described 9th not gate is connected to the second input of described second NAND gate, the output of described second NAND gate is connected to the input of the tenth not gate, the output of described tenth not gate is connected to the grid of the second DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described second DMOS pipe is connected with source electrode,
Second electric capacity, the first end of described second electric capacity is connected to the input of described 9th not gate, and the second end of described second electric capacity is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module;
First rest-set flip-flop, the S end of described first rest-set flip-flop is connected to the output of described tenth not gate, the R end of described first rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described first rest-set flip-flop is connected to the stiff end of the first analog switch, the selecting side of described first analog switch is connected to the input of the 11 not gate, the output of described 11 not gate is connected to the input of the 12 not gate, the output of described 12 not gate is connected to the input of the 13 not gate, the output of described 13 not gate is connected to the input of the 14 not gate, the output of described 14 not gate is connected to the S end of the second rest-set flip-flop, the R end of described second rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described second rest-set flip-flop is connected to the control end of described first analog switch,
Voltage comparator, the positive input terminal of described voltage comparator is connected to the selecting side of the second analog switch, the control end of described second analog switch is connected to the output of described 14 not gate, the stiff end of described second analog switch is connected to the anode of the first voltage source, the negative terminal of described first voltage source is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the negative input end of described voltage comparator is connected to the first end of described thermistor, second end of described thermistor is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the output of described voltage comparator is connected to the S end of the 3rd rest-set flip-flop, the R end of described 3rd rest-set flip-flop is connected to the low-pressure area power supply negative terminal of described Intelligent Power Module, the Q end of described 3rd rest-set flip-flop is connected to the control end of the 3rd analog switch, the stiff end of described 3rd analog switch is connected to the first end of described thermistor, first selecting side of described 3rd analog switch is as described first port, second selecting side of described 3rd analog switch is connected to the first end of the first resistance, second end of described first resistance is connected to the first selecting side of described 3rd analog switch,
4th analog switch, the control end of described 4th analog switch is connected to the input of described 13 not gate, the stiff end of described 4th analog switch is connected to the negative input end of described voltage comparator, the selecting side of described 4th analog switch is connected to the anode of the second voltage source, and the negative terminal of described second voltage source is connected to the power supply positive pole of described input circuit;
Output circuit, the power supply positive pole of described output circuit and negative pole are respectively as the higher-pressure region power supply positive pole of described self-checking circuit and negative pole, the first input end of described output circuit is connected to the drain electrode of described first DMOS pipe, second input of described output circuit is connected to the drain electrode of described second DMOS pipe, the output of described output circuit is as the output of described self-checking circuit, that described output circuit is used for that to be treated to the U phase higher-pressure region power supply negative terminal of described Intelligent Power Module by the pulse signal of described output circuit first input end and the pulse signal of the second input be benchmark and consistent with the input signal phase place of brachium pontis signal input part in the U phase of described Intelligent Power Module continuous signal,
5th analog switch, the stiff end of described 5th analog switch is connected to the output of described input circuit, the control end of described 5th analog switch is connected to the input of described 11 not gate, the selecting side of described 5th analog switch is connected to the grid of the 3rd DMOS pipe, the low-pressure area power supply negative terminal of described Intelligent Power Module is connected to after the substrate of described 3rd DMOS pipe is connected with source electrode, the drain electrode of described 3rd DMOS pipe is connected to the first end of the second resistance, and the second end of described second resistance is connected to the power supply positive pole of described output circuit.
3. Intelligent Power Module according to claim 1 and 2, is characterized in that, also comprises boostrap circuit, and described boostrap circuit comprises:
First bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described first bootstrap diode is connected to described U phase higher-pressure region power supply anode;
Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described Intelligent Power Module;
3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described Intelligent Power Module, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described Intelligent Power Module.
4. Intelligent Power Module according to claim 1 and 2, is characterized in that, also comprises:
Bridge arm circuit on three-phase, in each phase on described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase high-voltage district of described HVIC pipe;
Bridge arm circuit under three-phase, under each phase under described three-phase in bridge arm circuit, the input of bridge arm circuit is connected to the signal output part of corresponding phase in the three-phase low-voltage district of described HVIC pipe.
5. Intelligent Power Module according to claim 4, is characterized in that, in each phase described, bridge arm circuit comprises:
First power switch pipe and the first diode, the anode of described first diode is connected to the emitter of described first power switch pipe, the negative electrode of described first diode is connected to the collector electrode of described first power switch pipe, the collector electrode of described first power switch pipe is connected to the high voltage input of described Intelligent Power Module, the base stage of described first power switch pipe is as the input of bridge arm circuit in each phase described, and the emitter of described first power switch pipe is connected to the higher-pressure region power supply negative terminal of the corresponding phase of described Intelligent Power Module.
6. Intelligent Power Module according to claim 5, is characterized in that, under each phase described, bridge arm circuit comprises:
Second power switch pipe and the second diode, the anode of described second diode is connected to the emitter of described second power switch pipe, the negative electrode of described second diode is connected to the collector electrode of described second power switch pipe, the collector electrode of described second power switch pipe is connected to the anode of described first diode in corresponding upper bridge arm circuit, and the base stage of described second power switch pipe is as the input of bridge arm circuit under each phase described.
7. Intelligent Power Module according to claim 6, is characterized in that, the emitter of described second power switch pipe under each phase described in bridge arm circuit is as the low reference voltage end of the corresponding phase of described Intelligent Power Module.
8. the Intelligent Power Module according to any one of claim 5 to 7, is characterized in that, the voltage of the high voltage input of described Intelligent Power Module is 300V.
9. the Intelligent Power Module according to any one of claim 5 to 7, is characterized in that, is connected with filter capacitor in described HVIC pipe between the higher-pressure region power supply anode of each phase and higher-pressure region power supply negative terminal.
10. an air conditioner, is characterized in that, comprising: Intelligent Power Module as claimed in any one of claims 1-9 wherein.
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| CN201510641633.5A CN105226962B (en) | 2015-09-29 | 2015-09-29 | Intelligent power module and air conditioner |
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