CN105097767A - Semiconductor structure and semiconductor manufacturing process thereof - Google Patents
Semiconductor structure and semiconductor manufacturing process thereof Download PDFInfo
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- CN105097767A CN105097767A CN201410256889.XA CN201410256889A CN105097767A CN 105097767 A CN105097767 A CN 105097767A CN 201410256889 A CN201410256889 A CN 201410256889A CN 105097767 A CN105097767 A CN 105097767A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 179
- 238000000034 method Methods 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 208000019901 Anxiety disease Diseases 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000036506 anxiety Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 1
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor structure and a semiconductor manufacturing process thereof, which comprises the steps of forming a graphical conducting layer on a substrate, forming an undoped dielectric layer, forming a doped dielectric layer on the graphical conducting layer and the undoped dielectric layer, and carrying out an etching manufacturing process, wherein the top surface of the graphical conducting layer is flush with the top surface of the graphical conducting layer, the doped dielectric layer is formed on the graphical conducting layer and the undoped dielectric layer, and the etching manufacturing process has high etching selection ratio on the undoped dielectric layer and the doped dielectric layer, so that only the exposed doped dielectric layer in the etching manufacturing process can be completely etched, and the undoped dielectric layer cannot be etched.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, in more specific words it, it relates to a kind of semiconductor fabrication process forming through hole, and it can avoid the problem of dielectric layer eating thrown (punch).
Background technology
In the semiconductor structure, be electrically connected by interconnection structures such as interlayer connector (viaplug) or contact plungers (contactplug) between circuit layer with circuit layer, the plurality of interconnection structure generally forms interlayer through hole or contact through hole via in the first dielectric layer between the layers of etching process, inserts metal conductive materials more afterwards and is formed.Wherein the figure of above-mentioned through hole defines with a graphical photoresist, and the through-hole pattern defined also needs the effect that just can reach interconnection with the circuit layer exactitude position up and down for being connected.
So in implementation, for fear of board capacity limit, photoetching equipment formed photoresist figure time be inevitably bound to occur stack excursions (overlayshift) phenomenon, degree is heavy or light, defined through hole can be made cannot to be located in completely on desired circuit layer, and it likely can expose the other dielectric layer of circuit layer.Or in the design of some semiconductor circuits, the diameter of through hole is first in the sky is just greater than the width of circuit layer of institute for connecting, and the through hole after contraposition like this also will certainly expose the dielectric layer on circuit layer side.
Phenomenon common in above-mentioned prior art is formed in the step of through hole problem can occur at etching dielectric layer, because the etching process of through hole is using the circuit layer of below as etching stopping layer, if the through hole that etching is formed has expose the other dielectric layer of circuit layer, etching process can continue the dielectric layer that etching off exposes, and causes dielectric layer eating thrown (punch) to the problem of lower floor.So, the conductive plunger formed afterwards in through-holes likely can be electrically connected to the circuit structure of lower floor, causes the problem of element electrical property failure.
Summary of the invention
In order to aforementioned dielectric layer eating thrown problem of the prior art will be solved, the present invention is special to propose a kind of semiconductor fabrication process of novelty, it reaches to by doping dielectric layer has the characteristic of the etching selectivity of height with the dielectric layer that do not adulterate the effect optionally removing specific dielectric layer by etching process, and can not damage the dielectric layer at non-predetermined position.
An object of the present invention is to propose a kind of semiconductor structure, it comprises: a substrate, one patterned conductive layer is positioned in this substrate, one dielectric layer that do not adulterate to be positioned in this substrate and its end face flushes with the end face of this patterned conductive layer, and one to be positioned on this patterned conductive layer and this dielectric layer that do not adulterate by doping dielectric layer and the dielectric layer that do not adulterate with this patterned conductive layer and this contacts, wherein should expose this by this patterned conductive layer under doping dielectric layer by having in doping dielectric layer multiple through hole, this through hole of part exposes this by this patterned conductive layer under doping dielectric layer and this dielectric layer that do not adulterate simultaneously.
Another object of the present invention is to propose a kind of semiconductor fabrication process, its step comprises: provide a substrate, this substrate has a patterned conductive layer, form one and do not adulterate dielectric layer on this substrate, the end face of this dielectric layer that do not adulterate flushes with the end face of this patterned conductive layer, forming one does not adulterate on dielectric layer by doping dielectric layer at this patterned conductive layer and this, should contact by doping dielectric layer and this patterned conductive layer and this dielectric layer that do not adulterate, form a graphical photoresist at this by doping dielectric layer, this graphical photoresist has multiple through hole and exposes this by doping dielectric layer, those through holes some of simultaneously with this by this patterned conductive layer under the dielectric layer that adulterates and this dielectric layer that do not adulterate overlapping, and with this graphical photoresist for etching mask carries out an etching process, this etching process to this do not adulterate dielectric layer and should by doping dielectric layer have height etching selectivity, what make only to expose in this etching process should can by complete etching off by doping dielectric layer, this dielectric layer that do not adulterate can not be etched.
Far and away, this kind of object of the present invention and other objects will become more obvious read the preferred embodiment specification specified hereafter described with multiple diagram and drawing the person of readding after.
Accompanying drawing explanation
This specification constitutes the part of this specification containing drawings attached Yu Wenzhong, makes the person of readding have further understanding to the embodiment of the present invention.Those graphically depict some embodiments of the invention and together illustrate its principle together with describing herein.In those diagrams:
Fig. 1-Fig. 5 is the schematic cross-section of semiconductor fabrication process step in one embodiment of the present invention; And
Fig. 6 is the top view of several connector skew of embodiment of the present invention aspect.
Should be noted that all diagrams in this specification are all legend character, in order to know and conveniently illustrate event, each parts in diagram may be exaggerated or be presented with reducing in size and ratio, generally speaking, identical in figure reference symbol can be used for indicating revises element characteristics corresponding or similar in rear or different embodiment.
Symbol description
100 substrates
102 grid structures
104 insulation structure of shallow groove
106 source/drains
108 contact plungers
109 dielectric layers
110 patterned conductive layer
112 do not adulterate dielectric layer
112a position
114 by doping dielectric layer
114a ~ 114d position
115 conductive through holes
116 graphical photoresists
117 through holes
118 conductive plungers
Embodiment
In details hereafter describes, component symbol can be indicated in the diagram of enclosing the part become wherein, and represents with the special case describing mode of this embodiment practicable.This kind of embodiment can illustrate that enough details make the general technology personage in this field be able to tool to implement.The person of readding need recognize in the present invention the embodiment that also can utilize other or make under the prerequisite not departing from described embodiment structural, logicality and electrically on change.Therefore, details hereafter describes and will not limit for being considered to be one, otherwise wherein comprised embodiment is defined by the claim of enclosing.
Please refer to Fig. 1-Fig. 5, it shows the schematic cross-section of semiconductor fabrication process step according to one preferred embodiment of the present invention.First, as shown in Figure 1, provide a substrate 100 that basis is set as semiconductor structure of the present invention.Substrate 100 can be a silicon base, one contains silicon base, silicon base (such as GaN-on-silicon) is covered in one three five races or a Graphene covers the semiconductor bases such as silicon base (graphene-on-silicon).Then, form insulation structure of shallow groove (shallowtrenchisolation, STI) 104 in substrate 100, it defines multiple element area in substrate.Be formed with a grid structure 102 in each element area, its both sides then define source/drain 106.Substrate 100 is formed with a dielectric layer 109 with the top of grid structure 102, as a metal inner-dielectric-ayer (inter-metaldielectric, IMD), its material can be oxide, as silica or carbon-doped oxide, silicon nitride, or organic polymer, as perfluorocyclobutane or polytetrafluoroethylene, fluorine silex glass (fluorosilicateglass, FSG), organic silicate glass (organosilicateglass, OSG), or low-k dielectric material etc., as follows normal pressure chemical vapor phase deposition (SACVD) manufacture craft can be used to be formed, with cover completely below grid structure 102 and the space filled up therebetween.
Multiple with reference to Fig. 1.The top of dielectric layer 109 is formed with a patterned conductive layer 110, as a first metal layer (Metal1).Patterned conductive layer 110 can carry out the mode that photoetching process defines its line pattern again and formed via first being formed a metal level.Then be electrically connected with the contact plunger 108 be formed in dielectric layer 109 between patterned conductive layer 110 and the source/drain 106 of below.Contact plunger 108 can be formed via the mode inserting conductive metal material after form through hole in dielectric layer 109 again.
Then please refer to Fig. 2.Dielectric layer 109 is formed one not adulterate dielectric layer 112.The material of dielectric layer 112 of not adulterating can be the tetraethoxysilane (tetraethylorthosilicate, TEOS) of any ion that do not adulterate, and its end face flushes with the end face of patterned conductive layer 110.In this embodiment, the dielectric layer 112 that do not adulterate can use high density plasma CVD (HDPCVD) manufacture craft first to deposit and cover on dielectric layer 109 and patterned conductive layer 110, carry out a planarization manufacture craft more afterwards, as cmp (CMP) manufacture craft, remove the dielectric layer 112 that do not adulterate of part, make patterned conductive layer 110 out exposed and the end face of patterned conductive layer 110 is flushed with the end face of the dielectric layer 112 that do not adulterate.
After formation patterned conductive layer 110 and the dielectric layer 112 that do not adulterate, then please refer to Fig. 3, patterned conductive layer 110 and the dielectric layer 112 that do not adulterate form one by doping dielectric layer 114.Material by doping dielectric layer 114 can be the tetraethoxysilane (tetraethylorthosilicate being mixed with admixture, TEOS), as arsenic doped (As), boron (B), fluorine (F) or other conventional admixtures, but phosphorus (P) admixture forms phosphoric acid due to the water that can absorb in air, there is the anxiety of corroding metal layer, therefore do not advise using.In this embodiment, can the mode such as using plasma assistant chemical vapor deposition (PECVD) manufacture craft or aumospheric pressure cvd (APCVD) the manufacture craft mode that is mixed with the tetraethoxysilane of admixture at the Direct precipitation on dielectric layer 112 and patterned conductive layer 110 that do not adulterate be formed by doping dielectric layer 114.Or, in other embodiments, can adopt not adulterating by doping dielectric layer 114 that dielectric layer 112 and patterned conductive layer 110 first to deposit another dielectric layer that do not adulterate (not shown, it also can be integrally formed with the dielectric layer 112 that do not adulterate of below), carry out ion implantation manufacture craft afterwards again and do not adulterate this another and mix the mode of above-mentioned admixture in dielectric layer and formed.
After formation is by doping dielectric layer 114, then please refer to Fig. 4, form graphical photoresist 116 by doping dielectric layer 114.Formed in graphical photoresist 116 multiple through hole 117 expose below by doping dielectric layer 114, those through holes 117 are used in subsequent manufacturing processes, define the through-hole interconnection pattern by doping dielectric layer 114, therefore the position of through hole 117 is set to that meeting is overlapping with the patterned conductive layer 110 of below.Should be noted, in implementation, inevitable stack excursions (overlayshift) cause during owing to forming graphical photoresist 116, through hole 117 can not completely accurately on the position be positioned at set by us.According to the light and heavy degree of stack excursions, it may have several situations shown in Fig. 4, as aligning, the serious skew of position 114b, the skew a little etc. of position 114c completely of position 114a, wherein the drift condition shown in the 114b of position has seriously been attended the meeting overlapping with the dielectric layer 112 that do not adulterate of part arround patterned conductive layer 110.Easily in follow-up etching process, there is eating thrown (punch) problem and injure the circuit structure of below in the such position of similar 114b.In addition, in some specific configuration, through hole be likely be designed to be greater than its for the line construction of interconnection, as shown in the position 114d in Fig. 4, the diameter of its through hole has been greater than the patterned conductive layer of lower floor for interconnection, and this situation also can cause the situation of eating thrown to occur.Above-mentioned several drift condition can more clearly understand from structure shown in Fig. 6, conductive plunger 118a ~ 118d aspect that after it shows the lead to the hole site of several kenel of Fig. 4, extended meeting is formed.
After the graphical photoresist 116 of formation, then please refer to Fig. 5, with graphical photoresist 116 for etching mask carries out an etching process to form conductive through hole 115 in by doping dielectric layer 114.Should be noted in the present invention, this etching process to do not adulterate dielectric layer 112 and by doping dielectric layer 114 have height etching selectivity, also namely this etching process, to being subject to the etch-rate of doping dielectric layer 114 far above the etch-rate to the dielectric layer 112 that do not adulterate, can reach more than several times.So, as the position 112a in Fig. 5, even if the position 114a of the serious stack excursions phenomenon of aforementioned generation is because exposing by removing of dielectric layer 114 of doping the dielectric layer 112 that do not adulterate, what this exposed do not adulterate dielectric layer 112 position also can not be able to can be etched as etching stopping layer because of comparatively etch resistant, thus avoids the problem of dielectric layer eating thrown to occur.In conductive through hole 115, insert metal conductive materials afterwards, conductive plunger 118a ~ 118d as shown in Figure 6 can be become.
The explanation of comprehensive above-described embodiment, a large advantage of known semiconductor fabrication process of the present invention is, forms the easy steps being subject to doping dielectric layer, can solve dielectric layer eating thrown problem of the prior art by one.Also therefore effect, the stack excursions scope of tolerable more enough and to spare in manufacture craft, and the size of conductive plunger and metal level can be freer unrestricted, it contributes to the degree of freedom promoting manufacture craft ability and line design.
According to the semiconductor fabrication process that the invention described above provides, the present invention also provides a kind of semiconductor structure of novelty in this, its structure comprises: a kind of semiconductor structure, comprise: a substrate 100, one patterned conductive layer 110 is positioned in substrate 100, one dielectric layer 112 that do not adulterate to be positioned in substrate 100 and its end face flushes with the end face of patterned conductive layer 110, and one by doping dielectric layer 114 be positioned at patterned conductive layer 110 and on the dielectric layer 112 that do not adulterate and with contact, wherein expose by having multiple conductive through hole 114b in doping dielectric layer 114 patterned conductive layer 110 be subject to below doping dielectric layer 114, the conductive through hole 114b of part exposes patterned conductive layer 110 and the dielectric layer 112 that do not adulterate simultaneously.Contact plunger or interlayer connector can be filled with in addition in conductive through hole 114b.
The foregoing is only the preferred embodiments of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. a semiconductor structure, comprises:
Substrate;
Patterned conductive layer, is positioned in this substrate;
Do not adulterate dielectric layer, to be positioned in this substrate and its end face flushes with the end face of this patterned conductive layer; And
By doping dielectric layer, to be positioned on this patterned conductive layer and this dielectric layer that do not adulterate and to contact with this patterned conductive layer and this dielectric layer that do not adulterate, wherein should expose this by this patterned conductive layer under doping dielectric layer by having in doping dielectric layer multiple through hole, this through hole of part exposes this by this patterned conductive layer under doping dielectric layer and this dielectric layer that do not adulterate simultaneously.
2. semiconductor structure as claimed in claim 1, wherein this through hole is contact hole (contact) or interlayer hole (via).
3. semiconductor structure as claimed in claim 1, wherein should by doping dielectric layer for this dielectric layer that do not adulterate mix admixture after and formed.
4. semiconductor structure as claimed in claim 1, wherein this dielectric layer that do not adulterate is tetraethoxysilane (tetraethylorthosilicate, TEOS).
5. semiconductor structure as claimed in claim 1 should be wherein the tetraethoxysilane of arsenic doped, boron or fluorine by doping dielectric layer.
6. semiconductor structure as claimed in claim 1, separately comprises contact plunger or interlayer connector is inserted in this through hole.
7. semiconductor structure as claimed in claim 1, wherein the diameter of this through hole is greater than the width of patterned metal layer.
8. a semiconductor fabrication process, comprises:
One substrate is provided, this substrate has a patterned conductive layer;
Form one and do not adulterate dielectric layer on this substrate, the end face of this dielectric layer that do not adulterate flushes with the end face of this patterned conductive layer;
Forming one does not adulterate on dielectric layer by doping dielectric layer at this patterned conductive layer and this, should contact by doping dielectric layer and this patterned conductive layer and this dielectric layer that do not adulterate;
Form a graphical photoresist at this by doping dielectric layer, this graphical photoresist has multiple through hole and exposes this by doping dielectric layer, those through holes some of simultaneously with this by this patterned conductive layer under the dielectric layer that adulterates and this dielectric layer that do not adulterate overlapping; And
With this graphical photoresist for etching mask carries out an etching process, this etching process to this do not adulterate dielectric layer and should by doping dielectric layer have height etching selectivity, what make only to expose in this etching process should can by complete etching off by doping dielectric layer, and this dielectric layer that do not adulterate can not be etched.
9. semiconductor fabrication process as claimed in claim 8, wherein the do not adulterate step of dielectric layer of this formation one comprises:
This substrate and this patterned conductive layer deposit this dielectric layer that do not adulterate; And
Carry out this dielectric layer that do not adulterate that a planarization manufacture craft removes part, make this patterned conductive layer out exposed and the do not adulterate end face of dielectric layer of the end face of this patterned conductive layer and this is flushed.
10. semiconductor fabrication process as claimed in claim 8, wherein this formation one comprises by the step of doping dielectric layer:
Forming another this dielectric layer that do not adulterate does not adulterate on dielectric layer at this patterned conductive layer and this; And
Carry out an ion implantation manufacture craft not adulterate this another in dielectric layer and mix admixture.
11. semiconductor fabrication process as claimed in claim 8, wherein should be formed with plasma auxiliary chemical vapor deposition (PECVD) manufacture craft or aumospheric pressure cvd (APCVD) manufacture craft by doping dielectric layer.
12. semiconductor fabrication process as claimed in claim 8, wherein this dielectric layer that do not adulterate is formed with high density plasma CVD (HDPCVD) manufacture craft.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103117362A TWI531007B (en) | 2014-05-16 | 2014-05-16 | Semiconductor structure and semiconductor process thereof |
| TW103117362 | 2014-05-16 |
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| Publication Number | Publication Date |
|---|---|
| CN105097767A true CN105097767A (en) | 2015-11-25 |
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| CN201410256889.XA Pending CN105097767A (en) | 2014-05-16 | 2014-06-10 | Semiconductor structure and semiconductor manufacturing process thereof |
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| TW (1) | TWI531007B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303447B1 (en) * | 2000-02-11 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an extended metal gate using a damascene process |
| CN1890795A (en) * | 2003-12-24 | 2007-01-03 | 英特尔公司 | Dual damascene rrocess using carbon doped and carbon free oxide layers |
| CN101038875A (en) * | 2002-06-14 | 2007-09-19 | 蓝姆研究公司 | Process for etching openings in dielectric layer |
| TWI351735B (en) * | 2007-05-18 | 2011-11-01 | Nanya Technology Corp | Memory device and fabrication method thereof |
| CN102725106A (en) * | 2010-06-30 | 2012-10-10 | 应用材料公司 | Endpoint control during chemical mechanical polishing by detecting interface between different layers through selectivity change |
-
2014
- 2014-05-16 TW TW103117362A patent/TWI531007B/en active
- 2014-06-10 CN CN201410256889.XA patent/CN105097767A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303447B1 (en) * | 2000-02-11 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an extended metal gate using a damascene process |
| CN101038875A (en) * | 2002-06-14 | 2007-09-19 | 蓝姆研究公司 | Process for etching openings in dielectric layer |
| CN1890795A (en) * | 2003-12-24 | 2007-01-03 | 英特尔公司 | Dual damascene rrocess using carbon doped and carbon free oxide layers |
| TWI351735B (en) * | 2007-05-18 | 2011-11-01 | Nanya Technology Corp | Memory device and fabrication method thereof |
| CN102725106A (en) * | 2010-06-30 | 2012-10-10 | 应用材料公司 | Endpoint control during chemical mechanical polishing by detecting interface between different layers through selectivity change |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201545239A (en) | 2015-12-01 |
| TWI531007B (en) | 2016-04-21 |
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