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CN104992950A - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN104992950A
CN104992950A CN201510307054.7A CN201510307054A CN104992950A CN 104992950 A CN104992950 A CN 104992950A CN 201510307054 A CN201510307054 A CN 201510307054A CN 104992950 A CN104992950 A CN 104992950A
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connecting portion
metal level
pattern
portion pattern
pixel electrode
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孔祥永
成军
刘晓娣
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201510307054.7A priority Critical patent/CN104992950A/zh
Publication of CN104992950A publication Critical patent/CN104992950A/zh
Priority to PCT/CN2016/079451 priority patent/WO2016192476A1/zh
Priority to US15/545,817 priority patent/US10186527B2/en
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Abstract

本发明公开了一种阵列基板及其制备方法、显示装置，该方法包括：在衬底上形成像素电极层、栅金属层和源漏金属层，所述像素电极层包括第一连接部图案，所述栅金属层包括第二连接部图案，并且所述源漏金属层包括第三连接部图案；其中，所述第一连接部图案与所述第二连接部图案叠置，所述第一连接部图案超出所述第二连接部图案的部分通过第一过孔与所述第三连接部图案电连接。通过将源漏金属层上的第三连接部图案与像素电极层上的第一连接部图案电连接，取代了将源漏金属层上的第三连接部图案与栅金属层上的第二连接部图案电连接，有效避免了由于第二连接部图案采用低电阻特性的材料时，因其表面氧化影响导电性能的问题。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
近年来，显示技术得到了快速的发展，在以液晶显示器(LiquidCrystal Display，简称LCD)为代表的显示技术领域中，由于分辨率的提高和显示尺寸的增大、以及显示装置中驱动器电路的集成需要进行低电阻布线，因此，具有低电阻特性的金属例如铜(Cu)所制得的栅线和数据线、以及薄膜晶体管(Thin Film Transistor，简称TFT)中的栅极、源极和漏极已经应用于显示装置。
然而由于具有低电阻特性的金属例如Cu的活性比较强，如果采用Cu制得的栅线、其他配线等导电连接部件时，在刻蚀过程中Cu表面容易发生氧化，导致接触不良，影响了导电部件的导电性能。
发明内容
针对现有技术中的缺陷，本发明提供了一种阵列基板及其制备方法、显示装置，避免了由于导电部件采用低电阻特性的材料时，因其表面氧化影响导电性能的问题。
第一方面，本发明提供一种阵列基板的制备方法，包括：在衬底上形成像素电极层、栅金属层和源漏金属层，所述像素电极层包括第一连接部图案，所述栅金属层包括第二连接部图案，并且所述源漏金属层包括第三连接部图案；
其中，所述第一连接部图案与所述第二连接部图案叠置，所述第一连接部图案超出所述第二连接部图案的部分通过第一过孔与所述第三连接部图案电连接。
可选的，所述方法还包括：
在所述像素电极层和所述栅金属层之间形成导电缓冲层。
可选的，所述方法还包括：
在所述栅金属层上形成光刻胶层；
利用灰阶掩膜板通过曝光显影工艺后形成完全曝光区域、未曝光区域以及灰度曝光区域，去掉所述完全曝光区域的光刻胶，以及灰度曝光区域的部分光刻胶；
刻蚀所述完全曝光区域对应的像素电极层、导电缓冲层和栅金属层；
利用所述灰阶掩膜板去掉所述灰度曝光区域的光刻胶；
刻蚀所述灰度曝光区域对应的导电缓冲层和栅金属层，形成像素电极图案和第一连接部图案；
去掉所述未曝光区域的光刻胶，形成栅极图案和第二连接部图案。
可选的，所述方法还包括：
形成栅绝缘层和刻蚀阻挡层；
在所述栅绝缘层和刻蚀阻挡层预定第一连接部图案和第三连接部图案电连接的部分，形成用于使所述第一连接部图案与所述第三连接部图案电连接的第一过孔。
第二方面，本发明还提供了一种阵列基板，包括：衬底、像素电极层、栅金属层和源漏金属层，所述像素电极层包括第一连接部图案，所述栅金属层包括第二连接部图案，并且所述源漏金属层包括第三连接部图案；
其中，所述第一连接部图案与所述第二连接部图案叠置，所述第一连接部图案超出所述第二连接部图案的部分通过第一过孔与所述第三连接部图案电连接。
可选的，所述阵列基板还包括：设置在所述像素电极层和所述源漏金属层之间的刻蚀阻挡层和栅绝缘层，所述第一过孔贯穿所述刻蚀阻挡层和栅绝缘层。
可选的，所述阵列基板还包括：设置在所述像素电极层和所述栅金属层之间的导电缓冲层。
可选的，所述导电缓冲层的材质为钼铌合金或钛。
可选的，设置在所述源漏金属层的源极图案或漏极图案通过贯穿所述刻蚀阻挡层和栅绝缘层的第二过孔与设置在所述像素电极层的像素电极图案电连接。
可选的，所述栅金属层和所述源漏金属层的材质均为铜。
第三方面，本发明还提供了一种显示装置，包括上述的阵列基板。
由上述技术方案可知，本发明提供的一种阵列基板及其制备方法、显示装置，通过将源漏金属层上的第三连接部图案与像素电极层上的第一连接部图案电连接，取代了将源漏金属层上的第三连接部图案与栅金属层上的第二连接部图案电连接，有效避免了由于第二连接部图案采用低电阻特性的材料时，因其表面氧化影响导电性能的问题。
附图说明
图1至图10为本发明一实施例提供的制备阵列基板的过程示意图；
其中附图标记说明：
1、衬底；2、像素电极层；3、导电缓冲层；4、栅金属层；5、光刻胶完全保留区域；6、光刻胶完全去除区域；7、光刻胶半保留区域；8、栅绝缘层；9、刻蚀阻挡层；10、有源层图案；11、源漏金属层；12、第一过孔；13、第二过孔；14、第三过孔；15、第四过孔；16、像素电极图案暴露区域；21、第一连接部图案；22、像素电极图案；41、第二连接部图案；42、栅极图案；111、第三连接部图案；112、源极图案；113、漏极图案。
具体实施方式
下面结合附图，对发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
本发明提供了一种阵列基板的制备方法，如图10所示，包括：在衬底1上形成像素电极层2、栅金属层4和源漏金属层11，像素电极层2包括第一连接部图案21，栅金属层4包括第二连接部图案41，并且源漏金属层11包括第三连接部图案111；
其中，第一连接部图案21与第二连接部图案41叠置，第一连接部图案21超出第二连接部图案41的部分通过第一过孔12与第三连接部图案111电连接。
注意，在本发明中，第二连接部图案和第三连接部图案可以为传输信号或电力的线路的一部分。
上述方法通过将源漏金属层11上的第三连接部图案111与像素电极层2上的第一连接部图案21电连接，取代了将源漏金属层11上的第三连接部图案111与栅金属层4上的第二连接部图案41电连接，有效避免了由于第二连接部41图案采用低电阻特性的材料(例如：Cu)且刻蚀连接过孔时，因Cu表面氧化影响导电性能的问题。
下面对上述阵列基板的制备方法的流程进行详细说明，该阵列基板的制备方法的流程可以包括以下步骤：
步骤S1、在衬底1上依次形成像素电极层2、导电缓冲层3和栅金属层4，如图1所示；
举例来说，上述的衬底1可以为玻璃基板、石英基板或有机树脂基板；像素电极层2的材质为透明导电金属(例如：ITO)，厚度控制在100-2000nm；导电缓冲层3形成在所述像素电极层2和栅金属层4之间，其材质为防止Cu氧化以及Cu扩散的材质，例如：钼铌合金(MoNb)或钛(Ti)等，厚度控制在10-100nm；栅金属层4材质为低电阻特性且活性较强的材质，例如铜或铜合金，本实施例均以Cu进行举例说明，厚度控制在100-600nm；上述各膜层的厚度可以依照实际情况进行适应性调整。
步骤S2、在栅金属层4上形成光刻胶层；
步骤S3、利用灰阶掩膜板通过曝光显影工艺后形成完全曝光区域、未曝光区域以及灰度曝光区域，去掉完全曝光区域的光刻胶(光刻胶完全去除区域6)，以及灰度曝光区域的部分光刻胶(光刻胶半保留区域7)，如图2所示；
可理解的是，灰阶掩膜板包括完全不透明部分、半透明部分和完全透明部分；例如一种灰阶掩膜板是在透明衬底材料上在某些区域形成不透光的遮光金属层，在另外一些区域形成半透光的遮光金属层，其他区域不形成任何遮光金属层；其中，半透光的遮光金属层的厚度小于完全不透光的遮光金属层的厚度，此外，还可以通过调节半透光的遮光金属层的厚度来改变半透光的遮光金属层对紫外光的透过率。
基于此，灰阶掩膜板的工作原理例如为：通过控制灰阶掩膜板上下不同区域处遮光金属层的厚度，使曝光在不同区域的透过光的强度有所不同，从而使光刻胶进行有选择性的曝光显影后，形成与灰阶掩膜板的完全不透明部分、半透明部分以及完全透明部分分别对应的未曝光区域、灰度曝光区域和完全曝光区域。
本实施例中所指的光刻胶均为正性光刻胶，可以为由感光树脂、增感剂和溶剂三种主要成分组成的对光敏感的混合液体。感光树脂经过光照后，在曝光区域能很快地发生光固化反应，后续通过特定的溶液可以将固化的感光树脂清洗掉。
步骤S4、刻蚀完全曝光区域对应的像素电极层2、导电缓冲层3和栅金属层4，如图3所示；
上述步骤S4可以理解为：通过湿刻工艺采用双氧水系刻蚀液将完全曝光区域对应的栅金属层4刻蚀掉，然后再通过干刻工艺采用干刻的气体可以为Cl2+BCl3，将完全曝光区域刻蚀掉栅金属层4之后漏出的导电缓冲层3刻蚀掉；最后再通过湿刻工艺采用草酸系列刻蚀液将完全曝光区域刻蚀掉导电缓冲层3之后漏出的像素电极层2刻蚀掉，最后在完全曝光区域对应的位置漏出衬底1。
步骤S5、利用灰阶掩膜板去掉灰度曝光区域的光刻胶，如图4所示。
其原理与步骤S3类似，将不再进行详细说明。
步骤S6、刻蚀灰度曝光区域对应的导电缓冲层3和栅金属层4，形成像素电极图案22和第一连接部图案21，如图5所示。
可理解的是，灰度曝光区域对应的导电缓冲层3和栅金属层4的刻蚀方法与步骤S4中的方法类似，将不再进行详细说明。
步骤S7、去掉未曝光区域的光刻胶(光刻胶完全保留区域5)，形成栅极图案42和第二连接部图案41，如图6所示。
上述第二连接部图案41可以为栅线、其他配线等导电连接部件。
在上述步骤S3-S7中，步骤S5中利用步骤S3中同一的灰阶掩膜板去掉灰度曝光区域剩余部分的光刻胶，从而使得只采用了一道光罩就形成了像素电极图案22、第一连接部图案21、栅极图案42和第二连接部图案41，减少了光罩的使用量。
步骤S8、形成栅绝缘层8，如图7所示。
步骤S9、在栅绝缘层8上形成有源层，并通过一次光罩形成有源层图案10，如图8所示。
有源层的材质为采用铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide，简称ITZO)、氧化铟(In2O3)、以及氧化锌(ZnO)等透明金属氧化物半导体材料中的至少一种，厚度控制在10-150nm。
步骤S10、形成刻蚀阻挡层9，并通过一次光罩形成第一过孔12、第二过孔13、第三过孔14、第四过孔15，并且可以形成像素电极图案暴露区域16，如图9所示。
步骤S11、形成源漏金属层11，并通过一次光罩形成第三连接部图案111、源极图案112和漏极图案113，如图10所示。
需要说明的是，若在步骤步骤S10中根据需要形成了像素电极图案暴露区域16，那么在上述步骤S11形成第三连接部图案111、源极图案112和漏极图案113之后，需要刻蚀掉沉积在像素电极图案暴露区域16的源漏金属层，以露出像素电极图案暴露区域16对应的像素电极图案22。
源漏金属层11可以为Mo、MoNb、Al、AlNd、Ti、Cu中的一种或多种材料形成的单层或多层复合叠层，优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
上述步骤S9-S11中通过一次光罩形成各层的不同图案或者过孔，可以理解为构图工艺，可指包括光刻工艺或包括光刻工艺以及可是步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩膜板、曝光机等形成图形的工艺。可理解的是，上述制备阵列基板的步骤中，仅需要通过4次光罩，因此，上述方法通过将源漏金属层11上的第三连接部图案111与像素电极层2上的第一连接部图案21电连接，取代了将源漏金属层11上的第三连接部图案111与栅金属层4上的第二连接部图案41电连接，有效避免了由于第二连接部41图案采用低电阻特性的材料(例如：铜或铜合金)且刻蚀连接过孔时，因铜或铜合金表面氧化影响导电性能的问题；并且上述方法在形成第一连接部的过程中，只采用了一道光罩就形成了像素电极图案22、第一连接部图案21、栅极图案42和第二连接部图案41，进而减少了光罩的使用量，节约了成本。
第一过孔12在栅绝缘层8和刻蚀阻挡层9预定第一连接部图案21和第三连接部图案111电连接的部分，主要用于使第一连接部图案21与第三连接部图案111电连接；第二过孔13在栅绝缘层8和刻蚀阻挡层9预定源极图案112或漏极图案113电连接的部分，主要用于使像素电极图案22与源极图案112或漏极图案113电连接；第三过孔14和第四过孔15在刻蚀阻挡层9预定源极图案112和漏极图案113与有源层图案10电连接的部分，主要用于使源极图案112和漏极图案113与有源层图案10电连接。上述源极图案112和漏极图案113的位置可以互换，具体根据电路中电流的流向来确定哪个图案为源极图案，哪个图案为漏极图案，本实施例不对其进行限定。
可理解的是，上述阵列基板制备过程中，各层比如像素电极层2、导电缓冲层3、栅金属层4、栅绝缘层8、刻蚀阻挡层9等可以通过真空沉积或磁控溅射的方式形成，本实施例不再进行详细说明。
另外，需要说明的是，像素电极层2可以理解为包括像素电极图案22或预形成像素电极图案22的层，栅金属层4可以理解为包括栅极图案42或预形成栅极图案42的层，源漏金属层11可以理解为包括源极图案112和漏极图案113或预形成源极图案112和漏极图案113的层。
本实施例还提供了一种阵列基板，如图10所示，包括：衬底1、像素电极层2、栅金属层4和源漏金属层11，像素电极层2包括第一连接部图案21，栅金属层4包括第二连接部图案41，并且源漏金属层11包括第三连接部图案111；
其中，第一连接部图案21与第二连接部图案41叠置，第一连接部图案21超出所述第二连接部图案41的部分通过第一过孔12与第三连接部图案111电连接。
上述栅金属层4和源漏金属层11材质为低电阻特性且活性较强的材质，例如铜或铜合金，本实施例均以Cu进行举例说明。
上述阵列基板中源漏金属层11上的第三连接部图案111与像素电极层2上的第一连接部图案21电连接，取代了源漏金属层11上的第三连接部图案111与栅金属层4上的第二连接部图案41电连接，有效避免了由于第二连接部41图案采用低电阻特性的材料(例如：Cu)且刻蚀连接过孔时，因Cu表面氧化影响导电性能的问题。
阵列基板还包括：设置在像素电极层2和源漏金属层11之间的刻蚀阻挡层9和栅绝缘层8，第一过孔12贯穿刻蚀阻挡层9和栅绝缘层8；设置在源漏金属层11的源极图案112或漏极图案113通过贯穿刻蚀阻挡层9和栅绝缘层8的第二过孔13与设置在像素电极层2的像素电极图案22电连接。
为了防止栅金属层4的Cu在刻蚀过程中被氧化，阵列基板还包括：设置在像素电极层2和栅金属层4之间的导电缓冲层3。其中，导电缓冲层3的材质为防止Cu被氧化或扩散的材质，例如钼铌合金或钛。
本实施例还提供了一种显示装置，包括如上述的阵列基板。
本实施例中的显示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围，其均应涵盖在本发明的权利要求和说明书的范围当中。

Claims (11)

1.一种阵列基板的制备方法，其特征在于，包括：在衬底上形成像素电极层、栅金属层和源漏金属层，所述像素电极层包括第一连接部图案，所述栅金属层包括第二连接部图案，并且所述源漏金属层包括第三连接部图案；
其中，所述第一连接部图案与所述第二连接部图案叠置，所述第一连接部图案超出所述第二连接部图案的部分通过第一过孔与所述第三连接部图案电连接。
2.根据权利要求1所述的方法，其特征在于，所述方法还包括：
在所述像素电极层和所述栅金属层之间形成导电缓冲层。
3.根据权利要求2所述的方法，其特征在于，所述方法还包括：
在所述栅金属层上形成光刻胶层；
利用灰阶掩膜板通过曝光显影工艺后形成完全曝光区域、未曝光区域以及灰度曝光区域，去掉所述完全曝光区域的光刻胶，以及灰度曝光区域的部分光刻胶；
刻蚀所述完全曝光区域对应的像素电极层、导电缓冲层和栅金属层；
利用所述灰阶掩膜板去掉所述灰度曝光区域的光刻胶；
刻蚀所述灰度曝光区域对应的导电缓冲层和栅金属层，形成像素电极图案和第一连接部图案；
去掉所述未曝光区域的光刻胶，形成栅极图案和第二连接部图案。
4.根据权利要求1所述的方法，其特征在于，所述方法还包括：
形成栅绝缘层和刻蚀阻挡层；
在所述栅绝缘层和刻蚀阻挡层预定第一连接部图案和第三连接部图案电连接的部分，形成用于使所述第一连接部图案与所述第三连接部图案电连接的第一过孔。
5.一种阵列基板，其特征在于，包括：衬底、像素电极层、栅金属层和源漏金属层，所述像素电极层包括第一连接部图案，所述栅金属层包括第二连接部图案，并且所述源漏金属层包括第三连接部图案；
其中，所述第一连接部图案与所述第二连接部图案叠置，所述第一连接部图案超出所述第二连接部图案的部分通过第一过孔与所述第三连接部图案电连接。
6.根据权利要求5所述的阵列基板，其特征在于，所述阵列基板还包括：设置在所述像素电极层和所述源漏金属层之间的刻蚀阻挡层和栅绝缘层，所述第一过孔贯穿所述刻蚀阻挡层和栅绝缘层。
7.根据权利要求5所述的阵列基板，其特征在于，所述阵列基板还包括：设置在所述像素电极层和所述栅金属层之间的导电缓冲层。
8.根据权利要求7所述的阵列基板，其特征在于，所述导电缓冲层的材质为钼铌合金或钛。
9.根据权利要求6所述的阵列基板，其特征在于，设置在所述源漏金属层的源极图案或漏极图案通过贯穿所述刻蚀阻挡层和栅绝缘层的第二过孔与设置在所述像素电极层的像素电极图案电连接。
10.根据权利要求5-9中任一项所述的阵列基板，其特征在于，所述栅金属层和所述源漏金属层的材质均为铜。
11.一种显示装置，其特征在于，包括如权利要求5-10中任一项所述的阵列基板。
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