CN104950768A - VME (Versa module Eurocard) bus based multi-board-card communication method of dual-stage lithography control system - Google Patents
VME (Versa module Eurocard) bus based multi-board-card communication method of dual-stage lithography control system Download PDFInfo
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Abstract
The invention provides a VME (Versa module Euroboard card) bus based multi-board-card communication method of a dual-stage lithography control system, and belongs to the field of multi-board-card control and communication in the high-precision motion control field, and aims to solve the problems of poor real-time synchronization performance between multiple existing different types of board cards and an industrial control computer as well as incapacity of data interaction among the multiple board cards. According to the method, a VME bus module is applied, a master control CPU (central processing unit) board is taken as a master device of the VME bus, the other board cards are taken as slave devices, the master device can drive an address wire to select different slave devices for data interaction, and then the industrial control computer is connected with a main control board card through an internet access, so that the industrial control computer performs command transmission and data monitoring on each board card in real time. Communication among the different board cards is performed by taking the main control card as a bridge, and the master control CPU board firstly drives one board card requiring data transmission in the address wire, reads the data and then sends the data to the other board card needing to receive the data.
Description
Technical field
To the present invention relates to based on real-time Communication for Power between many boards of VME bus and industrial computer, and the method communicated between many boards, control and the communications field between the many boards belonging to high-precision motion control field.
Background technology
Litho machine double-workpiece-table scanning system is the Positioning Servo System high to requirement of real-time, and its requirement completes all operations such as scanning, exposure, photoetching within the 200us cycle.VME bus is made up of the electrical standard of Versa bus and mechanical framework two parts of European card (Eurocard), is a kind of asynchronous transmission bus.Because its numerous function, powerful compatibility and dynamic reconfiguration are widely used in military affairs, Aeronautics and Astronautics, medical treatment, transport and industrial control system.VME bus has the features such as high-performance, concurrency, real-time and high reliability, is the first-selection of real time embedded system always, is widely used in the communication of industrial computer and each board.The dissimilar board of existing polylith and the mutual interference existed when communicating between industrial computer, the problem of real-time synchronization performance difference, and the problem that between polylith board, data cannot be mutual.
Summary of the invention
The present invention seeks to solve the dissimilar board of existing polylith and the mutual interference existed when communicating between industrial computer, the problem of real-time synchronization performance difference, and the problem that between polylith board, data cannot be mutual, provide a kind of litho machine double-workpiece-table control system many boards communication means based on VME bus.
Litho machine double-workpiece-table control system many boards communication means based on VME bus of the present invention, many boards communicator that the method relates to comprises host computer, master cpu plate, VME bus and n from equipment plate card; N be more than or equal to 1 natural number;
Host computer: be connected with master cpu plate, for carrying out optimum configurations, instruction transmission and data monitoring to from equipment plate card;
Master cpu plate: be responsible for task scheduling, control the operation of whole communication, carries out data interaction by TCP/IP network communication protocol and host computer on the one hand, is communicated on the other hand by VME bus with n from equipment plate card;
VME bus: the intermediary communicated between board between two from equipment plate card and master cpu plate as n, VME bus is provided by VME industry control cabinet, and master cpu plate and n are individual is all be inserted in VME industry control cabinet from equipment plate card, and is connected by VME bus;
From equipment plate card: the control structure adopting DSP+FPGA, comprises VME P1/P2 module, level conversion CPLD module, FPGA module and DSP module from equipment plate card;
VME P1/P2 module is from the outside VME hardware of the Physical layer equipment plate card socket, is connected from equipment plate card by VMEP1/P2 module and VME bus;
Level conversion CPLD module completes the level conversion of FPGA module to VME P1/P2 module;
DSP module is communicated with FPGA module by the exterior storage expansion interface EMIF carried, FPGA module provides the data buffer area of a dual port RAM, communication data between DSP module and FPGA module is put into buffer memory in dual port RAM, and it is also be put into buffer memory in dual port RAM that master cpu plate and FPGA module carry out mutual data;
During communication, first master cpu plate resolves the instruction from host computer, if send data to a certain from equipment plate card, then master cpu plate performs VME write operation, data write in the dual port RAM that FPGA module from equipment plate card to be written provides by VME bus, then data are taken out by EMIF by DSP module again from dual port RAM; If think that reading is a certain from the data equipment plate card, then data should be put into buffer memory the dual port RAM that FPGA module provides from the DSP module of equipment plate card by EMIF, then master cpu plate performs VME read operation again and data is taken out from the dual port RAM of equipment plate card to be read and be sent to host computer display, realize thus host computer and n between equipment plate card and n from the communication between equipment plate card.
Advantage of the present invention: the present invention's application VME bus module, the main device module of VME bus is designed in master cpu plate, design in other boards VME bus from EM equipment module, main equipment is selected different to carry out data interaction from equipment by driving address wire, then industrial computer is connected with main controller by network interface, thus realize industrial computer real-time instruction transmission and data monitoring are carried out to each board.Communication between different board is then carry out using main controller as bridge, and first master cpu plate drives address wire to choose needs to send the board of data, and by digital independent out, and then these data are sent to another block need to receive in the board of these data.The dissimilar board of polylith does not interfere with each other with the phase that communicates between industrial computer, and real-time synchronization performance is good, and between polylith board, data can be carried out alternately.
Accompanying drawing explanation
Fig. 1 is the structural representation that the litho machine double-workpiece-table control system many boards communication means based on VME bus of the present invention relates to device; N=1;
Fig. 2 is the structural representation that the litho machine double-workpiece-table control system many boards communication means based on VME bus of the present invention relates to device; N > 1;
Fig. 3 provides the specific embodiment from equipment plate card;
Fig. 4 is the concrete structure schematic diagram of master cpu;
Fig. 5 is FPGA module inner VME bus logic Control timing sequence figure;
Fig. 6 is from equipment plate card intercommunication schematic diagram.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1 to Fig. 3, based on litho machine double-workpiece-table control system many boards communication means of VME bus described in present embodiment, many boards communicator that the method relates to comprises host computer 1, master cpu plate 2, VME bus 3 and n from equipment plate card 4; N be more than or equal to 1 natural number;
Host computer 1: be connected with master cpu plate 2, for carrying out optimum configurations, instruction transmission and data monitoring to from equipment plate card 4;
Master cpu plate 2: be responsible for task scheduling, control the operation of whole communication, carries out data interaction by TCP/IP network communication protocol and host computer 1 on the one hand, is communicated on the other hand by VME bus 3 with n from equipment plate card 4;
VME bus 3: the intermediary communicated between board between two from equipment plate card 4 and master cpu plate 2 as n, VME bus 3 is provided by VME industry control cabinet, master cpu plate 2 is all be inserted in VME industry control cabinet with n from equipment plate card 4, and is connected by VME bus;
From equipment plate card 4: the control structure adopting DSP+FPGA, comprises VME P1/P2 module 4-1, level conversion CPLD module 4-2, FPGA module 4-3 and DSP module 4-4 from equipment plate card 4;
VME P1/P2 module 4-1 is from the outside VME hardware of the Physical layer equipment plate card 4 socket, is connected from equipment plate card 4 by VME P1/P2 module 4-1 and VME bus 3;
Level conversion CPLD module 4-2 completes the level conversion of FPGA module 4-3 to VME P1/P2 module 4-1;
DSP module 4-4 is communicated with FPGA module 4-3 by the exterior storage expansion interface EMIF carried, FPGA module 4-3 provides the data buffer area of a dual port RAM, communication data between DSP module 4-4 and FPGA module 4-3 is put into buffer memory in dual port RAM, and it is also be put into buffer memory in dual port RAM that master cpu plate 2 and FPGA module 4-3 carry out mutual data;
During communication, first master cpu plate 2 resolves the instruction from host computer 1, if send data to a certain from equipment plate card 4, then master cpu plate 2 performs VME write operation, data write in the to be written dual port RAM that FPGA module 4-3 provides from equipment plate card 4 by VME bus, then data are taken out by EMIF by DSP module 4-4 again from dual port RAM; If think that reading is a certain from the data equipment plate card 4, then data should be put into buffer memory the dual port RAM that FPGA module 4-3 provides from the DSP module 4-4 of equipment plate card 4 by EMIF, then master cpu plate 2 performs VME read operation again and data is shown to be read taking out from the dual port RAM of equipment plate card 4 and be sent to host computer 1, realize thus host computer 1 and n between equipment plate card 4 and n from the communication between equipment plate card 4.
Due to the Transistor-Transistor Logic level that VME bus signals is 5V, and the I/O leg signal of FPGA is the LVTTL level of 3.3V, and therefore VME bus requirements could access FPGA after level conversion.Level switch module corresponding to VME P1 and P2 mouth adopts the CPLD with many level compatibility to realize, and the CPLD of employing is that the EPM3512A of the level of resistance to 5VTTL, level conversion CPLD module completes the level conversion of FPGA module to VMEP1/P2 module;
In present embodiment, substantially divide two kinds of situations from the quantity n of equipment plate card 4, n=1 and n > 1.
As n=1, as shown in Figure 1, this device only has one from equipment plate card 4, and master cpu plate 2 communicates from equipment plate card 4 by VME bus 3 and this are single.During communication, first master cpu plate 2 resolves the instruction from host computer 1, if send data to single from equipment plate card 4, then master cpu plate 2 performs VME write operation, data write in the single dual port RAM that FPGA module 4-3 provides from equipment plate card 4 by VME bus, then data are taken out by EMIF by DSP module 4-4 again from dual port RAM; If think that monitoring is single from the data equipment plate card 4, then data to be put into buffer memory in the dual port RAM that FPGA module 4-3 provides by EMIF by DSP module 4-4, and then master cpu plate 2 performs VME read operation again and data taken out from dual port RAM and be sent to host computer display.
As n > 1, as shown in Figure 2, this device has multiple from equipment plate card 4, and master cpu plate 2 is as main card, multiple from equipment plate card 4 as from card, realize main card and a certain communication between card or two from the communication between card by VME bus 3.Be synchro control card, data acquisition card, motion control card or safeguard protection card from the type of equipment plate card 4.Shown in Figure 3.On the basis of the single board of n=1, master cpu plate 2 is inserted VME industry control cabinet with polylith together with equipment plate card 4, set up from the connection between equipment plate card 4 and master cpu plate 2 by VME bus, thus indirectly establish from the connection between equipment plate card 4, complete the communication between many boards;
From single from equipment plate card to many boards, if do not add amendment, master cpu plate 2 so then can be caused can only to communicate from equipment plate card 4 with a certain, and can interference be there is, this is because other are from equipment plate card 4, also VME bus causes, so need to make certain amendment taking;
First, owing to all adopting the control structure of DSP+FPGA from equipment plate card 4, so the VME bus logic module in its FPGA module 4-3 can be designed to equally, but because master cpu plate 2 is according to identifying from the VME address of equipment plate card 4 and distinguishing from equipment plate card 4, so when designing the VME bus logic module in FPGA module 4-3, should be noted that and every block is arranged to not identical from the VME address of equipment plate card 4 inside;
Secondly, owing to having polylith from equipment plate card 4, in order to realize master cpu plate 2 can with any one piece interference-free from cartoon letters, so during communication, when the address wire data that master cpu plate 2 drives misfit from the address of card with this, namely, when the board that master cpu plate 2 is chosen is not this card, need this signal wire (the coherent signal line in FPGA and CPLD) that all VME are relevant from card to be all set to high-impedance state.So just can ensure at a time, what master cpu plate 2 was chosen can use relevant signal wire from card and not disturb by other board.
VME P1/P2 module 4-1 is that polylith is from the outside VME hardware interface of the Physical layer equipment plate card 4 (synchro control card, data acquisition card, motion control card and safeguard protection card); all kinds of board is all be inserted on VME industry control cabinet by P1 and the P2 mouth of VME, is connected by VME P1/P2 module and VME bus.
Realize communication to need to design the VME module on every block board.Here, using the main equipment of master cpu plate 2 as VME data bus, all kinds of board (data acquisition card, synchro control card, motion control card and safeguard protection card) conduct is from equipment.Because the main device module in master control board card designs, can use, so only need consider from EM equipment module by directly calling related system function after configuration.All adopt the control structure of DSP+FPGA from equipment plate card, the VME bus logic control module of its inside can be designed to similar, and suitably can simplify from EM equipment module under the prerequisite not affecting function.
In whole communication system, master cpu plate 2 is as master controller, and its task scheduling modules is responsible for dispatching and initiate all tasks that master control board card needs to perform, and comprises the task of needing the moment to run of instruction that host computer 1 sent by network and some planning.To the VME read or write that any one piece of board carries out, be also be responsible for initiation by master cpu plate 2 according to instruction.
Host computer 1 is directly connected with master cpu plate 2 by network interface, mainly realizes two functions, and one is carried out packing and be sent to master cpu plate 2 by the instruction and data that outside inputs, and comprises the parameters to all kinds of board and real time control command; Two is according to instruction, can read data in a certain piece of board in real time and carry out mapping monitoring.
Embodiment two: present embodiment is described further embodiment one, host computer 1 is that the program module of writing based on MFC framework realizes, master cpu plate 2 runs embedded real-time operating system, adopts the embedded real-time operating system such as VxWorks, WinCE or pSOS.
Embodiment three: present embodiment is described below in conjunction with Fig. 4, present embodiment is described further embodiment one, and master cpu plate 2 is responsible for control and the task scheduling of communications portion:
Master cpu plate 2 is the hinge of data transmission and the main device module of VME bus 3, VME bus 3 is controlled by master cpu plate 2, from the VME sequential that equipment plate card is all the initiation of cooperation master cpu plate 2 on communication, VME bus 3 itself has been a connection function, and the communication function module of master cpu plate 2 inside comprises network communication module, task scheduling modules, optimum configurations control module, data monitoring control module and VME module for reading and writing.
Task scheduling modules is responsible for initiation and the deletion of task in whole communication process, coordinates whole communication process.Master cpu plate 2 runs at the beginning, and its network communication module will be set up network with host computer 1 and be connected, and receives, resolves, performs the instruction of host computer 1 according to network communication protocol.If instruction sends parameter or data to a certain from equipment plate card 4, the parameter of correspondence then can be resolved by the optimum configurations control module of master cpu plate 2, and by VME module for reading and writing, data is write this from the double-interface RAM buffer of equipment plate card 4; If a certain internal data from equipment plate card 4 is read in instruction, first data are read from the double-interface RAM buffer of equipment plate card 4 from this by VME module for reading and writing by master cpu plate 2, then by data monitoring control module, data are processed, and pressed network communication protocol packing and encapsulation, then send the data to host computer 1 by network communication module.
Embodiment four: present embodiment is described below in conjunction with Fig. 6, present embodiment is described further embodiment one, FPGA module 4-3 inside is provided with EMIF interface logic biock and VME bus logic module, and these two logic modules share a dual port RAM simultaneously;
From the communication mode between equipment plate card 4 inner DSP module 4-4 and FPGA module 4-3 be:
Be inserted into VME industry control cabinet from equipment plate card 4 by VME P1/P2 module 4-1, during communication, first its FPGA module 4-3 is set up by VME bus logic module and outside VME bus 3 and contacts, and then FPGA module 4-3 sets up communication by its EMIF interface logic biock and DSP module 4-4;
When master cpu plate 2 writes data to this from equipment plate card 4, the VME bus logic module in FPGA module 4-3 is by digital independent and be deposited in dual port RAM, DSP module 4-4 then by EMIF interface by the data reading process in dual port RAM.When master cpu plate 2 carries out read operation, process and write operation are just in time contrary.If a certain internal data from equipment plate card 4 is read in instruction, master cpu plate 2 first by VME module for reading and writing by data reading from equipment plate card 4 buffer memory from correspondence, then by data monitoring control module, data are processed, and pressed network communication protocol packing and encapsulation, then send the data to host computer 1 by network communication module.
Embodiment five: present embodiment is described below in conjunction with Fig. 5, present embodiment is described further embodiment one, adopt state machine to realize from the VME bus logic module of the FPGA module 4-3 inside of equipment plate card 4, each VME address from equipment plate card 4 inside is set to different; During communication, when the address wire data that master cpu plate 2 drives are with when will carry out the misfitting from the address of equipment plate card 4 of read operation, n the signal wire that all VME are relevant from equipment plate card 4 is all set to high-impedance state.
VME bus logic module adopts Verilog HDL language syllogic state machine to realize, and whole state machine comprises 12 states.
State S0 represents Idle state, if the signal on S0 place address wire A [31..1], LWORD and address amendment line AM [5..0] is stablized, namely AS* becomes low level from high level, then enter S1 state;
In S1 state, judge the address on address bus, if address is misfitted from the address of equipment with this, then forward S12 state to, then get back to Idle state S0 place and continue to wait for, if address coincide, then enter S2 state;
In S2 state, judge whether word length line LWORD* is whether low level and address amendment line AM [5..0] mate (determining whether 0x09 here), if all correct, enter into S3 state, otherwise jumps to S12 state;
In S3 state, reception IACK* is high level, and namely select DTB pattern, do not use interruption, enter into S4 state, S4 directly enters into S5 state;
In S5 state, according to the height of the WRITE* signal level received, enter into the read-write cycle respectively.If WRITE* is low level, then enters into S6 state and start write cycle time, otherwise enter into S9 state and start the read cycle;
In S6 state, if DS1* and DS0* is low level, then enter into S7 state;
In S7 state, the direction of internal data bus is set to input, and the data be put on external data bus D [31..0] are read into and deposited in dual port RAM by master cpu plate, the address of dual port RAM can directly control with low eight of VME bus address, also can allocation address in addition.Enter into S8 state after data write dual port RAM completes, dragged down by DTACK*, enter into S12 state after DS1* and DS0* becomes high level in S8 state, release DTACK* signal wire, write cycle time terminates;
In S9 state, if DS1* and DS0* is low level, then enter into S10 state;
In S10 state, the direction of internal data bus is set to output, and the data reading of corresponding address in dual port RAM is put on external data bus, then enter into S11 state.Dragged down by DTACK* in S11 state, enter into S12 state after DS1* and DS0* becomes high level, release data line and DTACK* signal wire, the read cycle terminates;
When S12 state, state machine gets back to again Idle state S0, waits for VME read-write operation next time.
Claims (6)
1. based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, many boards communicator that the method relates to comprises host computer (1), master cpu plate (2), VME bus (3) and n from equipment plate card (4); N be more than or equal to 1 natural number;
Host computer (1): be connected with master cpu plate (2), for carrying out optimum configurations, instruction transmission and data monitoring to from equipment plate card (4);
Master cpu plate (2): be responsible for task scheduling, control the operation of whole communication, carry out data interaction by TCP/IP network communication protocol and host computer (1) on the one hand, communicated from equipment plate card (4) with n by VME bus (3) on the other hand;
VME bus (3): the intermediary communicated between board between two from equipment plate card (4) and master cpu plate (2) as n, VME bus (3) is provided by VME industry control cabinet, master cpu plate (2) and n is all be inserted in VME industry control cabinet from equipment plate card (4), and is connected by VME bus;
From equipment plate card (4): the control structure adopting DSP+FPGA, comprises VME P1/P2 module (4-1), level conversion CPLD module (4-2), FPGA module (4-3) and DSP module (4-4) from equipment plate card (4);
VME P1/P2 module (4-1) is from the outside VME hardware of the Physical layer equipment plate card (4) socket, is connected from equipment plate card (4) by VME P1/P2 module (4-1) and VME bus (3);
Level conversion CPLD module (4-2) completes the level conversion of FPGA module (4-3) to VME P1/P2 module (4-1);
DSP module (4-4) is communicated with FPGA module (4-3) by the exterior storage expansion interface EMIF carried, FPGA module (4-3) provides the data buffer area of a dual port RAM, communication data between DSP module (4-4) and FPGA module (4-3) is put into buffer memory in dual port RAM, and it is also be put into buffer memory in dual port RAM that master cpu plate (2) and FPGA module (4-3) carry out mutual data;
During communication, the instruction from host computer (1) first resolved by master cpu plate (2), if send data to a certain from equipment plate card (4), then master cpu plate (2) performs VME write operation, data write in the to be written dual port RAM that FPGA module (4-3) provides from equipment plate card (4) by VME bus, then data are taken out by EMIF by DSP module (4-4) again from dual port RAM; If think that reading is a certain from the data equipment plate card (4), then data should be put into buffer memory the dual port RAM that FPGA module (4-3) provides from the DSP module (4-4) of equipment plate card (4) by EMIF, then master cpu plate (2) performs VME read operation again and data is taken out from the dual port RAM of equipment plate card (4) to be read and be sent to host computer (1) display, realize thus host computer (1) with n between equipment plate card (4) and n individual from the communication between equipment plate card (4).
2. according to claim 1 based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, host computer (1) is that the program module of writing based on MFC framework realizes, master cpu plate (2) runs embedded real-time operating system, adopts VxWorks, WinCE or pSOS embedded real-time operating system.
3., according to claim 1 based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, be synchro control card, data acquisition card, motion control card or safeguard protection card from the type of equipment plate card (4).
4. according to claim 1 based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, master cpu plate (2) is responsible for control and the task scheduling of communications portion:
Master cpu plate (2) is the hinge that data are transmitted, its inside is provided with the main device module of VME bus (3), and the communication function module of master cpu plate (2) inside comprises network communication module, task scheduling modules, optimum configurations control module, data monitoring control module and VME module for reading and writing;
Task scheduling modules is responsible for initiation and the deletion of task in whole communication process, coordinates whole communication process.Master cpu plate (2) runs at the beginning, and its network communication module will be set up network with host computer (1) and be connected, and receives, resolves, performs the instruction of host computer (1) according to network communication protocol.If instruction sends parameter or data to a certain from equipment plate card (4), the parameter of correspondence then can be resolved by the optimum configurations control module of master cpu plate (2), and should from the double-interface RAM buffer of equipment plate card (4) by data write by VME module for reading and writing; If a certain internal data from equipment plate card (4) is read in instruction, first data are then read from the double-interface RAM buffer of equipment plate card (4) from this by VME module for reading and writing by master cpu plate (2), then by data monitoring control module, data are processed, and pressed network communication protocol packing and encapsulation, then send the data to host computer (1) by network communication module.
5. according to claim 1 based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, FPGA module (4-3) inside is provided with EMIF interface logic biock and VME bus logic module, and these two logic modules share a dual port RAM simultaneously;
From the communication mode between equipment plate card (4) inner DSP module (4-4) and FPGA module (4-3) be:
Be inserted into VME industry control cabinet from equipment plate card (4) by VME P1/P2 module (4-1), during communication, its FPGA module (4-3) first sets up contact by VME bus logic module and outside VME bus (3), and then FPGA module (4-3) sets up communication by its EMIF interface logic biock and DSP module (4-4);
When master cpu plate (2) writes data to this from equipment plate card (4), VME bus logic module in FPGA module (4-3) is by digital independent and be deposited in dual port RAM, DSP module (4-4) then by EMIF interface by the data reading process in dual port RAM.When master cpu plate (2) carries out read operation, process and write operation are just in time contrary.
6. according to claim 5 based on litho machine double-workpiece-table control system many boards communication means of VME bus, it is characterized in that, adopt state machine to realize from the VME bus logic module that the FPGA module (4-3) of equipment plate card (4) is inner, each VME address inner from equipment plate card (4) is set to different; During communication, when the address wire data that master cpu plate (2) drives are with when will carry out the misfitting from the address of equipment plate card (4) of read operation, n the signal wire that all VME are relevant from equipment plate card (4) is all set to high-impedance state.
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| CN112783136A (en) * | 2020-12-28 | 2021-05-11 | 东北轻合金有限责任公司 | 3950mm hot rolling mill control system and test method |
| CN113534931A (en) * | 2021-07-15 | 2021-10-22 | 上海泛腾电子科技有限公司 | Multifunctional control system based on VME bus architecture |
| CN113983924A (en) * | 2021-10-27 | 2022-01-28 | 北京航天巨恒系统集成技术有限公司 | Coordinate calculation system, method and device of multi-axis laser interferometer |
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| CN116560305B (en) * | 2023-06-13 | 2023-10-03 | 哈尔滨工业大学 | High-speed precise control device and method for multi-axis motion table |
| CN117454299A (en) * | 2023-12-21 | 2024-01-26 | 深圳市研盛芯控电子技术有限公司 | Abnormal node monitoring method and system |
| CN117454299B (en) * | 2023-12-21 | 2024-03-26 | 深圳市研盛芯控电子技术有限公司 | Abnormal node monitoring method and system |
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