[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN104900510B - 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 - Google Patents

刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 Download PDF

Info

Publication number
CN104900510B
CN104900510B CN201510369469.7A CN201510369469A CN104900510B CN 104900510 B CN104900510 B CN 104900510B CN 201510369469 A CN201510369469 A CN 201510369469A CN 104900510 B CN104900510 B CN 104900510B
Authority
CN
China
Prior art keywords
thickness
photoresist
etching
arc
shallow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510369469.7A
Other languages
English (en)
Other versions
CN104900510A (zh
Inventor
许进
冯奇艳
任昱
吕煜坤
张旭升
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201510369469.7A priority Critical patent/CN104900510B/zh
Publication of CN104900510A publication Critical patent/CN104900510A/zh
Priority to US15/083,292 priority patent/US9666472B2/en
Application granted granted Critical
Publication of CN104900510B publication Critical patent/CN104900510B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本发明提供一种刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法,包括如下步骤:在进行工艺前建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型,在进行光刻胶抗反射涂层工艺时,实时量测光刻胶抗反射涂层的厚度,并根据量测反馈的光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。本发明引入光学线宽测量仪(Optical Critical Dimension,简称OCD)检测量化光刻胶抗反射涂层的厚度,以改进浅槽隔离刻蚀线宽,并调整浅沟槽隔离刻蚀时间,从而精确控制浅沟槽隔离的关键尺寸。

Description

刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法
技术领域
本发明涉及半导体制造领域,涉及一种浅槽隔离刻蚀线宽刻蚀的方法,尤其涉及一种引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法。
背景技术
本领域技术人员清楚,完整的电路是由分离的器件通过特定的电学通路连接起来的,因此在集成电路制造中必须能够把器件隔离开来,这些器件随后还要能够互连以形成所需要的特定的电路结构。随着半导体器件尺寸的减小,浅沟槽隔离的关键尺寸对器件的电性影响和最终的良率越来越敏感。隔离不好会造成漏电、击穿低、闩锁效应等。因此,隔离技术是集成电路制造中的一项关键技术。
在65nm及以下的工艺技术中,为提高电路性能,获得更高的器件密度,使用和发展了浅沟槽隔离技术,沟槽的关键尺寸对器件电学性能和合格率有着极其重要的影响:
第一、随着半导体器件关键尺寸的减小,浅槽隔离尺寸的精准性对器件的电性影响越来越敏感,而且在有些区域,当尺寸发生很小变化时,电性可能会产生突变;如图1所示。
第二、沟槽的尺寸对产品的良率或最终的稳定性也有巨大影响:当浅沟槽尺寸在某极限区间变化时,会导致器件合格率的急剧下降甚至到零,甚至导致器件产品的直接报废,如图2所示。
并且,在浅沟槽隔离工艺技术日趋成熟的同时,通常在执行浅沟槽隔离工艺时存在着以下的一些问题:
①、在不同涂胶转速的工艺条件下,传统量测方法只能量测光刻胶顶部的线宽,不能量测光刻胶抗反射涂层的厚度,无法得到光刻胶抗反射涂层厚度和浅沟槽关键尺寸间的关系,从而导致工艺过程中或工艺结束后浅沟槽关键尺寸较难满足工艺的预期效果;
②、在产品曝光时,由于曝光机台本身偏移等原因,也会使光刻胶的线宽和涂层厚度发生偏移;
③、在产品刻蚀的过程中,由于刻蚀腔体的氛围,参数的漂移等不确定因素的改变,也容易造成沟槽顶部的关键尺寸远离设定的规格;
④、特别是在光刻机和刻蚀机台同时变化的情况下,会导致在线无法判断浅沟槽的尺寸变化根源,在线产品无法顺利流通和监控,这无疑会给生产带来巨大的损失。
为解决上述问题,目前业界通常采用扫描电子显微镜(scanning electronmicroscope,简称CDSEM)来测量浅槽隔离刻蚀线宽;然而,扫描电子显微镜是应用电子束在样品表面扫描激发二次电子成像的电子显微镜。
然而,在实用过程中,上述监控测量技术存在如下弊端:
①、只能一个时期量测一条线宽,存在效率偏低的问题;
②、由于无法测量光刻胶厚度,就无法准确反馈光刻胶形貌的实际信息,更没有办法根据反馈信息调整工艺条件,达到浅槽隔离刻蚀线宽尺寸得到精确控制的效果。
发明内容
为了克服以上问题,本发明旨在提供一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,以及采用该映射模型进行控制浅槽隔离刻蚀关键尺寸的方法;其引入光学线宽测量仪(Optical Critical Dimension,简称OCD)检测量化光刻胶抗反射涂层的厚度,以改进浅槽隔离刻蚀线宽,并调整浅沟槽隔离刻蚀时间,从而精确控制浅沟槽隔离的关键尺寸。
为实现上述目的,本发明的技术方案如下:本发明提供一种控制浅槽隔离刻蚀关键尺寸的方法,包括如下两个步骤:
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与所述转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
优选地,所述关键尺寸为浅槽隔离刻蚀线宽。
优选地,所述实时量测是采用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度。
优选地,所述步骤S2具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺转速的速率,实时选择和调整合适的喷涂工艺时间;
步骤S24:在所述工艺转速的速率下,根据所选择的所述喷涂工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
优选地,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
优选地,所述步骤S2中根据不同的底部抗反射涂层的厚度和选择的刻蚀时间的关系为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺整理转速的速率。
为实现上述目的,本发明还提供一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,所述步骤包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速,获得与所述转速相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。
从上述技术方案可以看出,本发明通过利用光学线宽测量仪检测量化工作区光刻胶抗反射涂层的厚度,建立厚度和浅沟槽线宽之间的关系,并通过调整浅槽隔离刻蚀线宽控制步骤的刻蚀时间,及时有效判断并反馈调整浅沟槽隔离刻蚀的关键线宽,从而精确控制浅沟槽顶部线宽,改变以往只能根据光刻胶的线宽来调控浅沟槽隔离线宽的缺点,降低受到量测干扰而带来的判断误差,大大提高浅沟槽隔离开发效率和产品良率的方法。
附图说明
图1为现有技术中不同线宽对应器件饱和电流影响的示意图
图2为现有技术中不同线宽对应器件合格率影响的示意图
图3为本发明引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法较佳实施例的流程示意图
图4为本发明引入的光学线宽测量仪工作原理示意图
图5为采用光学线宽测量仪(OCD)测量线宽和采用扫描电子显微镜(CDSEM)两种不同测量方式得到测量结果的比较示意图
图6为本发明在不同光刻胶抗反射涂层(BARC)厚度下得到相同浅沟槽线宽示意图
具体实施方式
体现本发明特征与优点的实施例将在后段的说明中详细叙述。应理解的是本发明能够在不同的示例上具有各种的变化,其皆不脱离本发明的范围,且其中的说明及图示在本质上当作说明之用,而非用以限制本发明。
以下结合附图3-6,通过具体实施例对本发明的控制浅槽隔离刻蚀关键尺寸的方法进一步详细说明。需说明的是,附图均采用非常简化的形式、使用非精准的比例,且仅用以方便、明晰地达到辅助说明本发明实施例的目的。
请参阅图3,图3为本发明引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法较佳实施例的流程示意图。如图所示,本发明提供一种控制浅槽隔离刻蚀关键尺寸的方法,包括如下两个步骤(步骤S1和步骤S2):
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
也就是说,本发明是先在进行工艺前建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型,并且通过利用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度,调整浅沟槽隔离刻蚀的时间,从而精确控制浅沟槽隔离的关键尺寸,改变以往只能粗略根据光刻胶线宽来调整浅沟槽线宽的缺点,做到在光刻胶抗反射涂层的厚度和线宽同时变化的情况下精确控制浅沟槽的关键尺寸,大大提高浅槽隔离开发效率和产品良率的方法。
具体地,在进行工艺前,需先建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的步骤S1:可以具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度。在本发明的实施例中,优选地,可以采用光学线宽测量仪(Optical Critical Dimension,简称OCD)来量测不同转速下得到的不同光刻胶抗反射涂层的厚度。
请参阅图4,图4为本发明引入的光学线宽测量仪工作原理示意图。如图所示,光学线宽测量仪,是通过分析吸收得到的从样品表面反射回来的光谱曲线所含的信息,以达到测量的目的。由于光学的特殊性质,其不仅可以测量样品的线宽,对测量膜厚和形貌等有十分强大的功能。
请参阅图5,图5为采用光学线宽测量仪(OCD)测量线宽和采用扫描电子显微镜(scanning electron microscope,简称CDSEM)两种不同测量方式得到测量结果的比较。如图所示,以往扫描电子显微镜CDSEM是应用电子束在样品表面扫描激发二次电子成像的电子显微镜,存在只能量测线宽,无法测量光刻胶厚度的弊端,因而无法准确反馈光刻胶形貌的实际信息。
采用OCD量测得到了线宽膜厚和形貌(例如,金属线上端和下端的斜率或夹角等),就可以执行如下步骤:
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸(浅槽隔离刻蚀线宽);
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。在本发明的实施例中,该映射关系模型可以为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
在本发明的实施例中,上述建立映射关系模型中所需的参数均可以采用光学线宽测量仪测量测量得到。有了上述测量参数后,就可以执行步骤S02,即在进行光刻胶抗反射涂层工艺时,实时量测光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的喷涂工艺条件,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
在本发明的一些实施例中,步骤S2可以具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺转速的速率,实时选择和调整合适的工艺时间;
步骤S24:在该工艺转速的速率下,根据所选择的工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
需要说明的是,预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式均属于现有技术,在此不再赘述。
较佳地,步骤S2中根据不同的底部抗反射涂层厚度和选择的刻蚀时间关系可以具体为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺时间调整(trim)时的转速速率。
请参阅图6,图6为本发明在不同光刻胶抗反射涂层(BARC)厚度下得到相同浅沟槽线宽示意图。如图所示,本发明实施例中,通过利用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度(如图中的TK1和TK2),调整浅沟槽隔离刻蚀线宽控制步骤的刻蚀时间t,从而精确控制浅槽隔离的关键尺寸CD,改变以往只能粗略根据光刻胶线宽来调整浅沟槽线宽的缺点,做到在光刻胶线宽和抗反射涂层厚度同时变化的情况下精确控制浅沟槽的关键尺寸,大大提高浅槽隔离开发效率和产品良率的方法。
图中的SIN&AA为氮化硅层和工作区(Activate Area)。
以上所述的仅为本发明的实施例,所述实施例并非用以限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。

Claims (7)

1.一种控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,包括如下两个步骤:
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与所述转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:采用光学线宽测量仪量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,采用光学线宽测量仪实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
2.根据权利要求1所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述关键尺寸为浅槽隔离刻蚀线宽。
3.根据权利要求1所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述步骤S2具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺整理转速的速率,实时选择和调整合适的工艺时间;
步骤S24:在所述工艺整理转速的速率下,根据所选择的所述喷涂工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
4.根据权利要求1-3任意一个所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
5.根据权利要求4所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述步骤S2中根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适工艺时间的关系为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺整理转速的速率。
6.一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,其特征在于,所述方法包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速,获得与所述转速相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:采用光学线宽测量仪量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。
7.根据权利要求6所述的方法,其特征在于,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
CN201510369469.7A 2015-06-29 2015-06-29 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 Active CN104900510B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201510369469.7A CN104900510B (zh) 2015-06-29 2015-06-29 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法
US15/083,292 US9666472B2 (en) 2015-06-29 2016-03-29 Method for establishing mapping relation in STI etch and controlling critical dimension of STI

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510369469.7A CN104900510B (zh) 2015-06-29 2015-06-29 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法

Publications (2)

Publication Number Publication Date
CN104900510A CN104900510A (zh) 2015-09-09
CN104900510B true CN104900510B (zh) 2018-01-26

Family

ID=54033105

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510369469.7A Active CN104900510B (zh) 2015-06-29 2015-06-29 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法

Country Status (2)

Country Link
US (1) US9666472B2 (zh)
CN (1) CN104900510B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10551165B2 (en) * 2015-05-01 2020-02-04 Adarza Biosystems, Inc. Methods and devices for the high-volume production of silicon chips with uniform anti-reflective coatings
TWI658349B (zh) * 2017-06-27 2019-05-01 亞智科技股份有限公司 製程監控方法與製程監控系統
CN108010869B (zh) * 2017-11-21 2020-09-29 上海华力微电子有限公司 一种精确控制浅沟槽隔离的整体形貌和性能的方法
CN108091560B (zh) * 2017-12-07 2020-04-10 上海华力微电子有限公司 优化不同透光率下浅槽隔离刻蚀形貌的方法
CN108063100B (zh) * 2017-12-08 2021-04-27 绍兴奥美电子科技有限公司 光刻胶去除工艺的测试方法
CN109637945B (zh) * 2018-12-19 2021-04-13 上海华力集成电路制造有限公司 半导体器件sti形貌的监控方法、其应用方法及改善tcr结构的方法
CN111276417B (zh) * 2020-02-20 2022-08-09 上海华力集成电路制造有限公司 一种控制接触孔刻蚀开口形貌的方法
CN115587545B (zh) * 2022-11-23 2023-04-07 广州粤芯半导体技术有限公司 一种用于光刻胶的参数优化方法、装置、设备及存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6808942B1 (en) * 2003-05-23 2004-10-26 Texas Instruments Incorporated Method for controlling a critical dimension (CD) in an etch process
CN101449363A (zh) * 2006-03-20 2009-06-03 应用材料公司 能用于形成低k双镶嵌集成电路的有机抗反射底涂层刻蚀工艺
CN103871954A (zh) * 2014-03-20 2014-06-18 上海华力微电子有限公司 一种优化浅槽隔离刻蚀线宽的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919259B2 (en) * 2002-10-21 2005-07-19 Taiwan Semiconductor Manufacturing Co., Ltd Method for STI etching using endpoint detection
JP3946724B2 (ja) * 2004-01-29 2007-07-18 シャープ株式会社 半導体装置の製造方法
JP2007294905A (ja) * 2006-03-30 2007-11-08 Hitachi High-Technologies Corp 半導体製造方法およびエッチングシステム
JP2008227360A (ja) * 2007-03-15 2008-09-25 Elpida Memory Inc 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6808942B1 (en) * 2003-05-23 2004-10-26 Texas Instruments Incorporated Method for controlling a critical dimension (CD) in an etch process
CN101449363A (zh) * 2006-03-20 2009-06-03 应用材料公司 能用于形成低k双镶嵌集成电路的有机抗反射底涂层刻蚀工艺
CN103871954A (zh) * 2014-03-20 2014-06-18 上海华力微电子有限公司 一种优化浅槽隔离刻蚀线宽的方法

Also Published As

Publication number Publication date
CN104900510A (zh) 2015-09-09
US20170025304A1 (en) 2017-01-26
US9666472B2 (en) 2017-05-30

Similar Documents

Publication Publication Date Title
CN104900510B (zh) 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法
CN103871954B (zh) 一种优化浅槽隔离刻蚀线宽的方法
US10998174B2 (en) Dry etching equipment and method for producing semiconductor device
US7348556B2 (en) Method of measuring three-dimensional surface roughness of a structure
CN104143519B (zh) 一种产品通孔刻蚀缺陷的检测方法
TWI593020B (zh) Plasma processing apparatus and plasma processing method
CN101207004A (zh) 半导体硅片刻蚀工艺的控制方法
TW201642343A (zh) 電漿處理裝置及電漿處理方法
KR20210134045A (ko) 반도체 디바이스에서의 파라미터-안정적 오정렬 측정 개선
CN104701212B (zh) 检测刻蚀负载效应的方法
US9224661B2 (en) Film thickness metrology
CN105304514A (zh) 一种半导体深孔刻蚀后的工艺监控方法
US7115426B2 (en) Method and apparatus for addressing thickness variations of a trench floor formed in a semiconductor substrate
JP4169004B2 (ja) 半導体装置の製造方法
CN105988310A (zh) 光刻方法及晶圆
CN116738512A (zh) 薄膜厚度模型的建立方法及设备
CN109560002A (zh) 晶圆翘曲程度的监控方法
CN108010869A (zh) 一种精确控制浅沟槽隔离的整体形貌和性能的方法
CN104617019B (zh) 一种GaAs衬底MHEMT栅凹槽腐蚀监控方法
CN106024758A (zh) 多晶硅栅极关键尺寸的先进控制方法
US11385187B1 (en) Method of fabricating particle size standards on substrates
Hakala et al. Automated gas-enhanced PFIB surface preparation enabled metrology and statistical analysis of 3D NAND devices
Park et al. Etch profile control of high-aspect ratio deep submicrometer/spl alpha/-Si gate etch
CN118629886A (zh) 一种利用对准标记测量晶圆全局槽深的方法及系统
CN102136419B (zh) 提高侧墙角均匀度的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant