CN104900510B - 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 - Google Patents
刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 Download PDFInfo
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- 239000003292 glue Substances 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
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- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本发明提供一种刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法,包括如下步骤:在进行工艺前建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型,在进行光刻胶抗反射涂层工艺时,实时量测光刻胶抗反射涂层的厚度,并根据量测反馈的光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。本发明引入光学线宽测量仪(Optical Critical Dimension,简称OCD)检测量化光刻胶抗反射涂层的厚度,以改进浅槽隔离刻蚀线宽,并调整浅沟槽隔离刻蚀时间,从而精确控制浅沟槽隔离的关键尺寸。
Description
技术领域
本发明涉及半导体制造领域,涉及一种浅槽隔离刻蚀线宽刻蚀的方法,尤其涉及一种引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法。
背景技术
本领域技术人员清楚,完整的电路是由分离的器件通过特定的电学通路连接起来的,因此在集成电路制造中必须能够把器件隔离开来,这些器件随后还要能够互连以形成所需要的特定的电路结构。随着半导体器件尺寸的减小,浅沟槽隔离的关键尺寸对器件的电性影响和最终的良率越来越敏感。隔离不好会造成漏电、击穿低、闩锁效应等。因此,隔离技术是集成电路制造中的一项关键技术。
在65nm及以下的工艺技术中,为提高电路性能,获得更高的器件密度,使用和发展了浅沟槽隔离技术,沟槽的关键尺寸对器件电学性能和合格率有着极其重要的影响:
第一、随着半导体器件关键尺寸的减小,浅槽隔离尺寸的精准性对器件的电性影响越来越敏感,而且在有些区域,当尺寸发生很小变化时,电性可能会产生突变;如图1所示。
第二、沟槽的尺寸对产品的良率或最终的稳定性也有巨大影响:当浅沟槽尺寸在某极限区间变化时,会导致器件合格率的急剧下降甚至到零,甚至导致器件产品的直接报废,如图2所示。
并且,在浅沟槽隔离工艺技术日趋成熟的同时,通常在执行浅沟槽隔离工艺时存在着以下的一些问题:
①、在不同涂胶转速的工艺条件下,传统量测方法只能量测光刻胶顶部的线宽,不能量测光刻胶抗反射涂层的厚度,无法得到光刻胶抗反射涂层厚度和浅沟槽关键尺寸间的关系,从而导致工艺过程中或工艺结束后浅沟槽关键尺寸较难满足工艺的预期效果;
②、在产品曝光时,由于曝光机台本身偏移等原因,也会使光刻胶的线宽和涂层厚度发生偏移;
③、在产品刻蚀的过程中,由于刻蚀腔体的氛围,参数的漂移等不确定因素的改变,也容易造成沟槽顶部的关键尺寸远离设定的规格;
④、特别是在光刻机和刻蚀机台同时变化的情况下,会导致在线无法判断浅沟槽的尺寸变化根源,在线产品无法顺利流通和监控,这无疑会给生产带来巨大的损失。
为解决上述问题,目前业界通常采用扫描电子显微镜(scanning electronmicroscope,简称CDSEM)来测量浅槽隔离刻蚀线宽;然而,扫描电子显微镜是应用电子束在样品表面扫描激发二次电子成像的电子显微镜。
然而,在实用过程中,上述监控测量技术存在如下弊端:
①、只能一个时期量测一条线宽,存在效率偏低的问题;
②、由于无法测量光刻胶厚度,就无法准确反馈光刻胶形貌的实际信息,更没有办法根据反馈信息调整工艺条件,达到浅槽隔离刻蚀线宽尺寸得到精确控制的效果。
发明内容
为了克服以上问题,本发明旨在提供一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,以及采用该映射模型进行控制浅槽隔离刻蚀关键尺寸的方法;其引入光学线宽测量仪(Optical Critical Dimension,简称OCD)检测量化光刻胶抗反射涂层的厚度,以改进浅槽隔离刻蚀线宽,并调整浅沟槽隔离刻蚀时间,从而精确控制浅沟槽隔离的关键尺寸。
为实现上述目的,本发明的技术方案如下:本发明提供一种控制浅槽隔离刻蚀关键尺寸的方法,包括如下两个步骤:
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与所述转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
优选地,所述关键尺寸为浅槽隔离刻蚀线宽。
优选地,所述实时量测是采用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度。
优选地,所述步骤S2具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺转速的速率,实时选择和调整合适的喷涂工艺时间;
步骤S24:在所述工艺转速的速率下,根据所选择的所述喷涂工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
优选地,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
优选地,所述步骤S2中根据不同的底部抗反射涂层的厚度和选择的刻蚀时间的关系为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺整理转速的速率。
为实现上述目的,本发明还提供一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,所述步骤包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速,获得与所述转速相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。
从上述技术方案可以看出,本发明通过利用光学线宽测量仪检测量化工作区光刻胶抗反射涂层的厚度,建立厚度和浅沟槽线宽之间的关系,并通过调整浅槽隔离刻蚀线宽控制步骤的刻蚀时间,及时有效判断并反馈调整浅沟槽隔离刻蚀的关键线宽,从而精确控制浅沟槽顶部线宽,改变以往只能根据光刻胶的线宽来调控浅沟槽隔离线宽的缺点,降低受到量测干扰而带来的判断误差,大大提高浅沟槽隔离开发效率和产品良率的方法。
附图说明
图1为现有技术中不同线宽对应器件饱和电流影响的示意图
图2为现有技术中不同线宽对应器件合格率影响的示意图
图3为本发明引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法较佳实施例的流程示意图
图4为本发明引入的光学线宽测量仪工作原理示意图
图5为采用光学线宽测量仪(OCD)测量线宽和采用扫描电子显微镜(CDSEM)两种不同测量方式得到测量结果的比较示意图
图6为本发明在不同光刻胶抗反射涂层(BARC)厚度下得到相同浅沟槽线宽示意图
具体实施方式
体现本发明特征与优点的实施例将在后段的说明中详细叙述。应理解的是本发明能够在不同的示例上具有各种的变化,其皆不脱离本发明的范围,且其中的说明及图示在本质上当作说明之用,而非用以限制本发明。
以下结合附图3-6,通过具体实施例对本发明的控制浅槽隔离刻蚀关键尺寸的方法进一步详细说明。需说明的是,附图均采用非常简化的形式、使用非精准的比例,且仅用以方便、明晰地达到辅助说明本发明实施例的目的。
请参阅图3,图3为本发明引入光学线宽测量仪以改进浅槽隔离刻蚀线宽的方法较佳实施例的流程示意图。如图所示,本发明提供一种控制浅槽隔离刻蚀关键尺寸的方法,包括如下两个步骤(步骤S1和步骤S2):
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
也就是说,本发明是先在进行工艺前建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型,并且通过利用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度,调整浅沟槽隔离刻蚀的时间,从而精确控制浅沟槽隔离的关键尺寸,改变以往只能粗略根据光刻胶线宽来调整浅沟槽线宽的缺点,做到在光刻胶抗反射涂层的厚度和线宽同时变化的情况下精确控制浅沟槽的关键尺寸,大大提高浅槽隔离开发效率和产品良率的方法。
具体地,在进行工艺前,需先建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的步骤S1:可以具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:量测不同转速下得到的不同光刻胶抗反射涂层的厚度。在本发明的实施例中,优选地,可以采用光学线宽测量仪(Optical Critical Dimension,简称OCD)来量测不同转速下得到的不同光刻胶抗反射涂层的厚度。
请参阅图4,图4为本发明引入的光学线宽测量仪工作原理示意图。如图所示,光学线宽测量仪,是通过分析吸收得到的从样品表面反射回来的光谱曲线所含的信息,以达到测量的目的。由于光学的特殊性质,其不仅可以测量样品的线宽,对测量膜厚和形貌等有十分强大的功能。
请参阅图5,图5为采用光学线宽测量仪(OCD)测量线宽和采用扫描电子显微镜(scanning electron microscope,简称CDSEM)两种不同测量方式得到测量结果的比较。如图所示,以往扫描电子显微镜CDSEM是应用电子束在样品表面扫描激发二次电子成像的电子显微镜,存在只能量测线宽,无法测量光刻胶厚度的弊端,因而无法准确反馈光刻胶形貌的实际信息。
采用OCD量测得到了线宽膜厚和形貌(例如,金属线上端和下端的斜率或夹角等),就可以执行如下步骤:
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸(浅槽隔离刻蚀线宽);
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。在本发明的实施例中,该映射关系模型可以为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
在本发明的实施例中,上述建立映射关系模型中所需的参数均可以采用光学线宽测量仪测量测量得到。有了上述测量参数后,就可以执行步骤S02,即在进行光刻胶抗反射涂层工艺时,实时量测光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的喷涂工艺条件,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
在本发明的一些实施例中,步骤S2可以具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺转速的速率,实时选择和调整合适的工艺时间;
步骤S24:在该工艺转速的速率下,根据所选择的工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
需要说明的是,预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式均属于现有技术,在此不再赘述。
较佳地,步骤S2中根据不同的底部抗反射涂层厚度和选择的刻蚀时间关系可以具体为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺时间调整(trim)时的转速速率。
请参阅图6,图6为本发明在不同光刻胶抗反射涂层(BARC)厚度下得到相同浅沟槽线宽示意图。如图所示,本发明实施例中,通过利用光学线宽测量仪检测量化光刻胶抗反射涂层的厚度(如图中的TK1和TK2),调整浅沟槽隔离刻蚀线宽控制步骤的刻蚀时间t,从而精确控制浅槽隔离的关键尺寸CD,改变以往只能粗略根据光刻胶线宽来调整浅沟槽线宽的缺点,做到在光刻胶线宽和抗反射涂层厚度同时变化的情况下精确控制浅沟槽的关键尺寸,大大提高浅槽隔离开发效率和产品良率的方法。
图中的SIN&AA为氮化硅层和工作区(Activate Area)。
以上所述的仅为本发明的实施例,所述实施例并非用以限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。
Claims (7)
1.一种控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,包括如下两个步骤:
步骤S1:在进行工艺前,建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型;具体包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速速率,获得与所述转速速率相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:采用光学线宽测量仪量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型;
步骤S2:在进行光刻胶抗反射涂层工艺时,采用光学线宽测量仪实时量测所述光刻胶抗反射涂层的厚度,并根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适的工艺时间,以使得在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
2.根据权利要求1所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述关键尺寸为浅槽隔离刻蚀线宽。
3.根据权利要求1所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述步骤S2具体包括:
步骤S21:预先建立不同的抗反射涂层的厚度和不同刻蚀时间得到相同浅沟槽线宽的关系式;
步骤S22:在进行光刻胶抗反射涂层工艺时,先量测所述光刻胶抗反射涂层的厚度;
步骤S23:根据量测反馈的所述光刻胶抗反射涂层厚度、映射关系模型和工艺整理转速的速率,实时选择和调整合适的工艺时间;
步骤S24:在所述工艺整理转速的速率下,根据所选择的所述喷涂工艺时间进行刻蚀工艺,以使在线晶圆产品在不同光刻胶抗反射涂层厚度下得到相同浅沟槽刻蚀关键尺寸。
4.根据权利要求1-3任意一个所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层(Bottom Anti Reflective Coating)的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
5.根据权利要求4所述的控制浅槽隔离刻蚀关键尺寸的方法,其特征在于,所述步骤S2中根据量测反馈的所述光刻胶抗反射涂层厚度及步骤S14得到映射关系模型,实时选择和调整合适工艺时间的关系为:
CDAEI=CDADI+CD1bias+d*t1
=CDADI+CD2bias+d*t2
其中,CDAEI为刻蚀前预定的关键尺寸,t1和t2为对应膜厚THK1和THK2的工艺整理时间,d为工艺整理转速的速率。
6.一种建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的映射关系模型的方法,其特征在于,所述方法包括:
步骤S11:通过调整工作区对晶圆产品进行光刻胶抗反射涂层喷涂工艺时的转速,获得与所述转速相应的具有不同厚度的光刻胶抗反射涂层;
步骤S12:采用光学线宽测量仪量测不同转速下得到的不同光刻胶抗反射涂层的厚度;
步骤S13:对具有不同抗反射涂层的厚度的晶圆产品使用同一支工艺菜单进行刻蚀,并收集所有晶圆刻蚀后的关键尺寸;
步骤S14:建立刻蚀前后线宽差与光刻胶抗反射涂层厚度对应的关系模型。
7.根据权利要求6所述的方法,其特征在于,所述映射关系模型为:
CD1bias=CD1AEI-CDADI
其中:CD1AEI为膜厚THK1刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD1bias为膜厚THK1刻蚀前后的关键尺寸差;
CD2bias=CD2AEI-CDADI
其中:CD2AEI为膜厚THK2刻蚀后的关键尺寸,CDADI为刻蚀前的关键尺寸,CD2bias为膜厚THK2刻蚀前后的关键尺寸差;
CD1bias=2*THK1/Ctg(angle)
CD2bias=2*THK2/Ctg(angle)
其中,THK1和THK2为不同的抗反射涂层的厚度;Ctg(angle)为抗反射涂层厚度的余切函数。
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