CN104743504A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN104743504A CN104743504A CN201310754040.0A CN201310754040A CN104743504A CN 104743504 A CN104743504 A CN 104743504A CN 201310754040 A CN201310754040 A CN 201310754040A CN 104743504 A CN104743504 A CN 104743504A
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Abstract
The invention discloses a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the following steps: providing a substrate, wherein a first conductive layer is arranged on the surface of the substrate, a sacrificial layer is arranged on the surface of the first conductive layer, a mask layer is arranged on the surface of the sacrificial layer, and the mask layer is exposed on part of the surface of the sacrificial layer; taking the mask layer as a mask, etching the sacrificial layer until the first conductive layer is exposed, and forming a first opening and a second opening in the sacrificial layer; forming conductive films on the surface of the mask layer and on the side walls and bottom surfaces of the first opening and the second opening; forming dielectric layers full of the first opening and the second opening on the surfaces of the conductive films; removing part of conductive films on the surface of the mask layer so as to pattern the conductive films after the dielectric layers are formed, forming a first plug in the first opening, forming a second plug in the second opening, and forming a second conductive layer on the surface of the mask layer, wherein the second plug and the second conductive layer are in electrical open circuit; and electrically connecting the second conductive layer with the first plug. Therefore, the performance of the formed semiconductor device is stable and good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor devices and forming method thereof.
Background technology
MEMS (Micro-Electro Mechanical System is called for short MEMS) is the integrated device of a kind of obtaining information, process information and executable operations.Sensor in MEMS can receive the external informations such as pressure, position, speed, acceleration, magnetic field, temperature or humidity, and obtained external information is converted to the signal of telecommunication, so that process in MEMS.Namely pressure sensor is a kind of switching device pressure signal being converted to the signal of telecommunication.
Capacitance pressure transducer, is the one in existing pressure sensor, and a kind of capacitance pressure transducer, of prior art comprises: substrate; Be positioned at the first electrode layer of substrate surface; Be positioned at the second electrode lay of substrate and the first electrode layer surface, have cavity between described first electrode layer and the second electrode lay, described cavity makes the first electrode layer and the second electrode lay electric isolution.
Described first electrode layer, the second electrode lay and cavity form capacitance structure, when described the second electrode lay is when being under pressure, can deformation be there is in described the second electrode lay, cause the distance between described first electrode layer and the second electrode lay to change, cause the capacitance of described capacitance structure to change.The pressure be subject to due to described the second electrode lay is corresponding with the capacitance of described capacitance structure, therefore, it is possible to the pressure be subject to by the second electrode lay is converted into the signal of telecommunication that described capacitance structure exports.
But, existing pressure sensor unstable properties.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor devices and forming method thereof, improves the performance of sensor.
For solving the problem, the invention provides a kind of formation method of semiconductor devices, comprising: substrate is provided, described substrate surface has the first conductive layer, described first conductive layer surface has sacrifice layer, and described sacrificial layer surface has mask layer, and described mask layer exposes partial sacrificial layer surface; With described mask layer for mask, etch described sacrifice layer, till exposing the first conductive layer, in sacrifice layer, form the first opening and the second opening; On described mask layer surface, the sidewall of the first opening and the second opening and lower surface form conducting film; The dielectric layer of filling full first opening and the second opening is formed on described conducting film surface; After formation dielectric layer, remove the partially conductive film on mask layer surface, with graphical described conducting film, the first connector is formed in the first opening, the second connector is formed in the second opening, form the second conductive layer on mask layer surface, described second connector and the second conductive layer electricity open circuit, described second conductive layer is electrically connected with the first connector.
Optionally, before formation second conductive layer, at sidewall and the lower surface formation protective layer of described sacrificial layer surface, the first opening and the second opening, described conducting film is formed at described protective layer.
Optionally, the material of described protective layer is titanium nitride.
Optionally, the thickness of described protective layer is 100 dust ~ 200 dusts.
Optionally, the material of described conducting film is titanium, tungsten, aluminium or copper.
Optionally, the thickness of described conducting film is 50 dust ~ 150 dusts.
Optionally, the first conductive layer electricity open circuit bottom the first conductive layer bottom the second connector and the first connector.
Optionally, the first conductive layer be connected with bottom the second connector is as bottom electrode, and described second conductive layer is top electrodes, and described first conductive layer, the second conductive layer, the first connector and the second connector form sensor.
Optionally, described first opening and the width of the second opening parallel in substrate surface direction are 200 dust ~ 300 dusts.
Optionally, the material of described sacrifice layer is different from the material of the first conductive layer, the second conductive layer and mask layer.
Optionally, the material of described sacrifice layer is amorphous carbon.
Optionally, the formation method of described dielectric layer comprises: at conducting film surface deposition deielectric-coating, and described deielectric-coating fills full described second opening; Deielectric-coating described in polishing, till the conducting film exposing mask layer surface.
Optionally, also comprise: after the partially conductive film removing mask layer surface, etch the mask layer exposed by described second conductive layer, till exposing sacrifice layer; After the described mask layer of etching, with the second conductive layer and mask layer for mask, adopt isotropic etching technics to etch described sacrifice layer, till exposing the first conductive layer, between described first conductive layer and the second conductive layer, form cavity.
Optionally, the material of described mask layer is one or more combinations in silica, silicon nitride, silicon oxynitride.
Optionally, described substrate comprises: the insulating barrier of electric interconnection structure and semiconductor devices described in semiconductor base, the semiconductor devices being positioned at semiconductor substrate surface or semiconductor base, the electric interconnection structure being electrically connected described semiconductor devices and electric isolution.
Optionally, described first conductive layer is electrically connected with described semiconductor devices by described electric interconnection structure.
Optionally, the material of described insulating barrier comprises humidity sensitive dielectric material.
Accordingly, the present invention also provides a kind of semiconductor devices adopting above-mentioned any one method to be formed, and comprising: substrate, the first conductive layer of described substrate surface; Be positioned at the sacrifice layer of described first conductive layer surface, described sacrificial layer surface has mask layer, has the first opening and the second opening that expose the first conductive layer in described sacrifice layer and mask layer; Be positioned at the first connector of the first opening; Be positioned at the second connector of the second opening, described second connector and the second conductive layer electricity open circuit; Be positioned at second conductive layer on mask layer surface, described second conductive layer is electrically connected with the first connector.
Compared with prior art, technical scheme of the present invention has the following advantages:
In formation method of the present invention, form the first opening and the second opening in sacrifice layer after, on described mask layer surface, the sidewall of the first opening and the second opening and lower surface form conducting film.Wherein, be positioned at the conducting film of the first opening for the formation of the first connector, be positioned at the conducting film of the second opening for the formation of the second connector, because the first opening and the second opening are formed by etching sacrificial layer, and etch described sacrifice layer and not easily produce etch by-products, therefore not easily quality is good at the described conducting film interface that contacts with the first conductive layer, i.e. contact resistance between the contact interface of described first connector or the second connector and the first conductive layer reduces.Secondly, be positioned at the conducting film on mask layer surface for the formation of the second conductive layer, described second conductive layer is electrically connected with the first connector, because described first connector and the second conductive layer are formed by conducting film, the contact resistance therefore between described first connector and the second conductive layer is low, electrical connection properties is good.Because described first connector and the top of the second connector or the contact resistance of bottom are all reduced, the operating current of therefore formed semiconductor devices improves, thus makes the stable performance of formed semiconductor devices.
Further, before formation second conductive layer, at sidewall and the lower surface formation protective layer of described sacrificial layer surface, the first opening and the second opening, described conducting film is formed at described protective layer.After follow-up formation first connector, the second connector and the second conductive layer, described protective layer can, in the process removing sacrifice layer, protect described first connector, the second connector and the second conductive layer surface from damage.
Further, the material of described sacrifice layer is amorphous carbon, the product etching described sacrifice layer is easy to volatilization, therefore form the first opening and the second opening in sacrifice layer after, can not can increase the etch by-products of resistance in the first conductive layer surface attachment, then the contact interface quality between the conducting film of follow-up formation and the first conductive layer is good.
In structure of the present invention, in described sacrifice layer and mask layer, there is the first opening and the second opening that expose the first conductive layer, in described first opening, there is the first connector, in described second opening, there is the second connector, second conductive layer on described mask layer surface, and described second conductive layer is electrically connected with the first connector.The interface contact resistance that the bottom of described first connector and the second connector contacts with the first conductive layer is lower, and electrical connection properties between the first connector and the second conductive layer is good.Therefore described semiconductor devices operating current improve, stable performance.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of sensor;
Fig. 2 to Fig. 7 is the cross-sectional view of the forming process of the semiconductor devices of the embodiment of the present invention.
Detailed description of the invention
As stated in the Background Art, existing pressure sensor unstable properties.
Fig. 1 is a kind of cross-sectional view of sensor, comprising: substrate 100; Be positioned at first electrode layer 101 on substrate 100 surface; Be positioned at the second electrode lay 102 on substrate 100 and the first electrode layer 101 surface, between described first electrode layer 101 and the second electrode lay 102, there is cavity 103; There is between described first electrode layer 101 and the second electrode lay 102 first conductive plunger 104 and the second conductive plunger 105, by insulating barrier electric isolution between described second conductive plunger 105 and the second electrode lay 102, and the first conductive plunger 104 is not connected with the first electrode layer 101 bottom the second conductive plunger 105; The sidewall surfaces of described first conductive plunger 104 and the second conductive plunger 105 has the first protective layer 106 and covers; Described the second electrode lay 102 and the first electrode layer 101 apparent surface have the second protective layer 107.
Described first conductive plunger 104 and the second conductive plunger 105 are suspended on the first electrode layer 101 surface for supporting the second electrode lay 102.Secondly, respectively bias voltage is applied to the first electrode layer 101 and the second electrode lay 102, obtain the capacitance variation amount of the capacitance structure that the first electrode layer 101, the second electrode lay 102 and cavity 103 are formed with this.In addition, described first conductive plunger 104 and the second conductive plunger 105 are electrically connected with the first electrode layer 101 respectively, and first the first electrode layer 101 of being connected with the second conductive plunger 105 of conductive plunger 104 open circuit mutually isolated by wet sensitive dielectric layer mutually, first electrode layer 101 of described mutual open circuit and wet sensitive dielectric layer form capacitance type humidity sensor, by applying bias voltage to the first conductive plunger 104 and the second conductive plunger 105, the capacitance variation amount of the capacitance structure that the first conductive layer 101 is formed with wet sensitive dielectric layer can be obtained.Therefore, described sensor can obtain outside pressure and humidity information simultaneously.
But, find through research, as shown in the region A in Fig. 1 and region B, easily there is process byproducts in top and the bottom of described first conductive plunger 104 or the second conductive plunger 105, the polymer that such as etching technics produces, the interface contact resistance causing described first conductive plunger 104 or the second conductive plunger 105 to contact with the first electrode layer 101 or the second electrode lay 102 increases, and the operating current of sensor is reduced, then the unstable properties of described sensor.
Concrete; when forming the sensor shown in Fig. 1; in described cavity 103, there is sacrifice layer; described second protective layer is formed at sacrificial layer surface; described after formation second protective layer; form the second electrode lay 102 at the second protective layer, and remove described sacrifice layer after formation the second electrode lay 102.
For region A; wherein; because the sidewall surfaces of described first conductive plunger 104 and the second conductive plunger 105 is covered by the first protective layer 106; therefore need first to be formed in sacrifice layer the first protection connector that the first conductive layer 101 contacts; etch described first protection connector; to form the through hole exposing the first conductive layer 101 in described first protection connector, in described through hole, filled conductive material is to form the first conductive plunger 104 and the second conductive plunger 105.Because the material of described first protective layer 106 is dielectric layer material; when etching described first protection connector to form through hole; the polymer that easy generation is not easily removed in a large number; described polymer can be attached to the first conductive layer 101 surface of via bottoms, causes the contact resistance between the bottom of the first conductive plunger 104 and the second conductive plunger 105 and the first conductive layer 101 to increase.
For region B; due to after formation second protective layer 107; the second electrode lay 102 is formed on the second protective layer 107 surface; and described the second electrode lay 102 needs to contact with the first conductive plunger 104; therefore, before formation the second electrode lay 102, described second protective layer 107 can be etched and expose the first conductive plunger 104 top.And the technique of described etching second protective layer 107 can produce the polymer not easily removed equally, described polymer can be attached to the first conductive plunger 104 top, causes the contact resistance between the first conductive plunger 104 and the second electrode lay 102 to increase.
In order to solve the problem, after further research, the present invention proposes a kind of formation method of semiconductor devices.Wherein, form the first opening and the second opening in sacrifice layer after, on described mask layer surface, the sidewall of the first opening and the second opening and lower surface form conducting film.Wherein, be positioned at the conducting film of the first opening for the formation of the first connector, be positioned at the conducting film of the second opening for the formation of the second connector, because the first opening and the second opening are formed by etching sacrificial layer, and etch described sacrifice layer and not easily produce etch by-products, therefore not easily quality is good at the described conducting film interface that contacts with the first conductive layer, i.e. contact resistance between the contact interface of described first connector or the second connector and the first conductive layer reduces.Secondly, be positioned at the conducting film on mask layer surface for the formation of the second conductive layer, described second conductive layer is electrically connected with the first connector, because described first connector and the second conductive layer are formed by conducting film, the contact resistance therefore between described first connector and the second conductive layer is low, electrical connection properties is good.Because described first connector and the top of the second connector or the contact resistance of bottom are all reduced, the operating current of therefore formed semiconductor devices improves, thus makes the stable performance of formed semiconductor devices.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 to Fig. 7 is the cross-sectional view of the forming process of the semiconductor devices of the embodiment of the present invention.
Please refer to Fig. 2, provide substrate 200, described substrate 200 surface has the first conductive layer 201, and described first conductive layer 201 surface has sacrifice layer 202, and described sacrifice layer 202 surface has mask layer 203, and described mask layer 203 exposes partial sacrificial layer 202 surface.
Described substrate 200 comprises: semiconductor base 210, be positioned at the insulating barrier 212 of electric interconnection structure 211 and semiconductor devices described in semiconductor base 210 surface or the semiconductor devices of semiconductor base 210, the electric interconnection structure 211 being electrically connected described semiconductor devices (not shown) and electric isolution.
In the present embodiment, described first conductive layer 201 and insulating barrier 212 can form humidity sensor.And, described first conductive layer 201 can and the second conductive layer of follow-up formation and the cavity between the first conductive layer 201 and the second conductive layer form pressure sensor, therefore formed semiconductor devices is the integrated device of pressure sensor and humidity sensor.
Described semiconductor devices can be cmos device, and described cmos device comprises transistor, memory, capacitor or resistor etc.Described semiconductor base 210 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate, such as gallium nitride or GaAs etc.In the present embodiment, the material of described insulating barrier 212 comprises humidity sensitive dielectric material, such as polyimides, and described insulating barrier 212 can as the dielectric layer in formed capacitance type humidity sensor.
In the present embodiment, described semiconductor base 200 is silicon substrate, and the semiconductor devices in described substrate 200 is transistor (not shown).The surface of described substrate 200 is insulating barrier 212 surface, and described first conductive layer 201 is formed in described substrate 200, and the surface of described first conductive layer 201 flushes with the surface of insulating barrier 212.
Described first conductive layer 201 is made up of at least two discrete the first sub-electrode layer (not shown), and mutually isolated by described insulating barrier 212 between described first sub-electrode layer; Follow-up the first formed connector and the second connector lay respectively at two the first discrete sub-electrode layer surfaces, described first connector and the second connector is enable to apply bias voltage to the first be connected sub-electrode layer respectively, thus obtain the capacitance variation amount of the capacitance structure that two the first sub-electrode layers and insulating barrier 212 are formed, the humidity information of external environment condition is obtained with this.
Secondly, described first conductive layer 201 can also as the bottom electrode of the pressure sensor of follow-up formation, second conductive layer of follow-up formation is as the top layer electrode of pressure sensor, follow-uply be formed at cavity between the first conductive layer 201 and the second conductive layer, namely form pressure inductor with described first conductive layer 201 and the second conductive layer, by obtaining the capacitance variation amount of the capacitance structure that the first conductive layer 201, second conductive layer and cavity are formed, the pressure information of external environment condition can be obtained.
The material of described first conductive layer 201 is conductive material, such as copper, tungsten or aluminium, and in the present embodiment, the material covering the partial insulative layer 212 surrounding described first conductive layer 201 is humidity sensitive dielectric material.Described first conductive layer 201 can also be electrically connected with described semiconductor devices by described electric interconnection structure 211.
Owing to there is cavity before the second conductive layer of follow-up formation and described first conductive layer 201, described cavity, the first conductive layer 201 and the second conductive layer is enable to form pressure sensor, therefore, before the second continuous after its formation conductive layer, sacrifice layer 202 is formed on described first conductive layer 201 surface, described sacrifice layer 202 for occupying the required correspondence position forming cavity, and after follow-up formation second conductive layer, removes described sacrifice layer 202 to form cavity.
In addition, in order to subsequent technique can form the first connector and the second connector on the first conductive layer 201 surface, need in described sacrifice layer 202, form the first opening and the second opening that expose the first conductive layer 201, therefore described sacrifice layer 202 surface is formed with the mask layer 203 defining the first opening and the second opening correspondence position.
The formation process of described sacrifice layer 202 is chemical vapor deposition method or physical gas-phase deposition.The material of described sacrifice layer 202 is different from the material of the first conductive layer 201 and mask layer 203, follow-up when removing sacrifice layer 202 to ensure, can not damage the first conductive layer 201 and mask layer 203.In the present embodiment, the material of described sacrifice layer 202 is amorphous carbon, because the etching gas of etching amorphous carbon comprises oxygen, described oxygen and carbon react can produce carbon monoxide or silica gas, therefore etching amorphous carbon not easily generates solid by-product, thus not easily causes the first conductive layer 201 surface topography bad after etching.
The formation process of described mask layer 203 comprises: at sacrifice layer 202 surface deposition mask film; Patterned photoresist layer is formed at mask film surface; With described photoresist layer for mask film described in mask etching is till exposing sacrifice layer 202 surface, form mask layer 203; After etch mask film, remove described photoresist layer.The material of described mask layer 203 is one or more combinations in silica, silicon nitride, silicon oxynitride.Described mask layer 203, except the mask as etching first opening and the second opening, can also, when follow-up removal sacrifice layer 202, protect the second conductive layer surface from damage, and dare to support described second conductive layer be suspended on first conductive layer 201 surface.
Please refer to Fig. 3, with described mask layer 203 for mask, etch described sacrifice layer 202, till exposing the first conductive layer 201, in sacrifice layer 202, form the first opening 204 and the second opening 205.
The technique of described etching sacrificial layer 202 is anisotropic dry etch process, can form the first opening 204 and the second opening 205 that sidewall is surperficial vertical relative to substrate 200, the width that the first opening 204 formed and the second opening 205 are parallel to substrate 200 surface direction is 200 dust ~ 300 dusts.In the present embodiment, the material of described sacrifice layer 202 is amorphous carbon, and described anisotropic dry etch process comprises: etching gas comprises oxygen, and power is greater than 100 watts, and bias voltage is greater than 100 volts, and temperature is greater than 100 degrees Celsius.
Material due to described sacrifice layer 202 is amorphous carbon, in described anisotropic dry etch process, described amorphous carbon can with oxygen reaction, generation CO gas or carbon dioxide are discharged, therefore etch described amorphous carbon and not easily produce solid byproducts, therefore the first conductive layer 201 clean surface of going out of the first opening 204 and the second opening 205 bottom-exposed, not there is etch by-products attachment, the follow-up contact interface resistance being formed at conducting film in the first opening 204 and the second opening 205 and the first conductive layer 201 is lower, the electric current being conducive to the semiconductor devices work that driving is formed improves, thus improve operating efficiency and the stability of the semiconductor devices formed.
The first opening 204 formed at subsequent technique for the formation of the first connector, described second opening 205 at subsequent technique for the formation of the second connector; And, the first conductive layer 201 bottom described second opening 205 and electricity open circuit between the first conductive layer 201 bottom the first opening 204.In the present embodiment, described first opening 204 and the second opening 205 expose two the first discrete sub-electrode layer surfaces respectively, then described two discrete the first sub-electrode layers are as two electrodes of humidity sensor, and between described two discrete the first sub-electrode layers for the insulating barrier 212 of isolating as the dielectric layer between two electrodes; Because between two the first sub-electrode layers, insulating barrier 212 material is wet sensitive dielectric material, therefore, by obtaining the capacitance variation between described two the first sub-electrode layers, the humidity of external environment condition can namely be obtained.And the first connector of follow-up formation and the second connector are respectively used to two discrete sub-electrode layer applying bias voltages, to obtain capacitance variation.
Please refer to Fig. 4, on described sacrifice layer 202 surface, the sidewall of the first opening 204 and the second opening 205 and lower surface form protective layer 206; Conducting film 207 is formed on described protective layer 206 surface.
Described conducting film 207 is for the formation of the first follow-up connector, the second connector and the second conductive layer; Wherein, the conducting film 207 being positioned at the first opening 204 is for the formation of the first connector, and the conducting film 207 being positioned at the second opening 205 is for the formation of the second connector, and the conducting film being positioned at mask layer 203 surface forms the second conductive layer.
Described protective layer 206 spreads in sacrifice layer 202 for preventing the material of conducting film 207, to ensure pattern and the stable performance of described conducting film 207 and sacrifice layer 202; And when the described sacrifice layer 202 of follow-up removal, described protective layer 206 can protect conducting film 207 surface being positioned at the first opening 204 and the second opening 205 from damage, to ensure the stable performance of formed semiconductor devices.
In the present embodiment, the material of described protective layer 206 is titanium nitride, and the material of described conducting film 207 is titanium.The thickness of described protective layer 206 is 100 dust ~ 200 dusts, and the thickness of described conducting film 207 is 50 dust ~ 150 dusts; In the present embodiment, the thickness of described protective layer 206 is 150 dusts, and the thickness of described conducting film 207 is 100 dusts.Owing to being positioned at the conducting film 207 on mask layer 203 surface for the formation of the second conductive layer; and the second conductive layer is after follow-up removal sacrifice layer 202; need to be suspended on the first conductive layer 201 surface; make to form cavity between the first conductive layer 201 and the second conductive layer; therefore the thickness of described conducting film 207 and protective layer 206 is not easily blocked up, to ensure that follow-up the second formed conductive layer can not fracture because quality is excessive.Because the resistivity of described titanium material is low, conductive capability good, even if the thinner thickness of described conducting film 207, also can ensure that the second conductive layer has low resistivity; And; the material of described protective layer 206 is titanium nitride; described titanium nitride also has conductive capability, and the laminated construction that conducting film 207 and protective layer 206 can be made further to form has low-resistivity, then enough large to meeting technical need by the electric current of described conducting film 207 and protective layer 206.
In other embodiments, the material of described conducting film can also be tungsten, aluminium or copper, and formation process is depositing operation, electroplating technology or chemical plating process.
The formation process of described protective layer 206 and conducting film 207 is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.In the present embodiment; the technique forming described protective layer 206 and conducting film 207 is physical gas-phase deposition; the parameter of described physical gas-phase deposition is: air pressure is that 10-7 holder ~ 10-9 holds in the palm, and base station temperature is-15 degrees Celsius ~-25 degrees Celsius, and substrate bias power is 300 watts ~ 900 watts.
Please refer to Fig. 5, formed on described conducting film 207 surface and fill full first opening 204(as shown in Figure 4) and the second opening 205(as shown in Figure 4) dielectric layer 208.
Described dielectric layer 208 for conducting film 207 and protective layer 206 being fixed on sidewall and the lower surface of the first opening 204 or the second opening 205, and can protect the conducting film 207 being positioned at the first opening 204 or the second opening 205.
The material of described dielectric layer 208 is one or more combinations in silica, silicon nitride, silicon oxynitride, low K dielectric material; The formation method of described dielectric layer 208 comprises: at conducting film 207 surface deposition deielectric-coating, and described deielectric-coating fills full described second opening 205; Deielectric-coating described in polishing, till the conducting film 207 exposing mask layer 203 surface.
Please refer to Fig. 6, after formation dielectric layer 208, remove the partially conductive film 207(on mask layer 203 surface as shown in Figure 5), with graphical described conducting film 207, the first connector 207a is formed at the first opening 204(as shown in Figure 4), the second connector 207b is formed at the second opening 205(as shown in Figure 4), the second conductive layer 207c is formed on mask layer 203 surface, described second connector 207a and the second conductive layer 207c electricity open circuit, described second conductive layer 207c is electrically connected with the first connector 207a.
The technique of described patterned conductive film 207 comprises: form photoresist layer at dielectric layer 208 and conducting film 207 surface; Described photoresist layer is exposed, to expose partially conductive film 207 surface; With described photoresist layer for mask, adopt anisotropic dry etch process to etch described conducting film 207 and protective layer 206, till exposing mask layer 203, form the second conductive layer 207c, the first connector 207a and the second connector 207b.It should be noted that, in the second conductive layer 207c formed, there is single or the some through hole or the opening that expose mask layer 203, sacrifice layer 202 can be removed from described through hole or opening so that follow-up.
Wherein, the first conductive layer 201 bottom second connector 207b and the first conductive layer 207 electricity open circuit bottom the first connector 207a, described first conductive layer 207 and insulating barrier 212 can as humidity sensors, and described first connector 207a and the second connector 207b is for driving two electrodes of humidity sensor.In the present embodiment, described first conductive layer 207 comprises at least two the first discrete sub-electrode layers, and described first connector 207a and the second connector 207c lays respectively at two discrete first sub-electrode layer surfaces, described two discrete the first sub-electrode layers are as two electrodes of humidity sensor, and described two electrodes can be subject to the driving of the first connector 207a and the second connector 207c.
Secondly, described first conductive layer 201 and the second conductive layer 207c can also for the formation of pressure sensors.Wherein, due to the second connector 207b and the second conductive layer 207c electricity open circuit, and be connected with part first conductive layer 201 bottom described second connector 207b, then with part first conductive layer 201 be connected bottom the second connector 207b as bottom electrode; And the second conductive layer 207c be connected with the first connector 207a is as top electrodes, after follow-up removal sacrifice layer 202, between described first conductive layer 201 and the second conductive layer 207c, form cavity.
Due in the present embodiment, described first connector 207 and the second conductive layer 207c are formed by conducting film 207, then between described first connector 207 and the second conductive layer 207c, electrical connection properties is good, the first connector 207 is low with the contact resistance of the second conductive layer 207c junction, then drive the semiconductor devices work formed current stabilization and enough greatly to meeting technical need.Therefore, the stable performance of the sensor formed.
Please refer to Fig. 7, after the partially conductive film removing mask layer 203 surface, etch the mask layer 203 exposed by described second conductive layer 207c, till exposing sacrifice layer 202; After the described mask layer 203 of etching, with the second conductive layer 207c and mask layer 203 for mask, adopt isotropic etching technics to etch described sacrifice layer 202, till exposing the first conductive layer 201, between described conductive layer 201 and the second conductive layer 207c, form cavity 209.
The technique of described etching mask layer 203 is anisotropic dry etch process, makes the mask layer after etching 203 figure consistent with the figure of the second conductive layer 207; After etching mask layer 203, expose sacrifice layer 202, and after removal sacrifice layer 202, the cavity 209 formed can with ft connection, insulating barrier 212 is made to touch external environment condition, because the material of described insulating barrier 212 is wet sensitive dielectric material, the dielectric coefficient of described insulating barrier 212 is changed along with the change of humidity, the capacitance change between two that then can obtain that described first connector 207a and the second connector 207b connects discrete the first conductive layers 201.
The technique etching described sacrifice layer 202 is isotropic etching technics, because the etch rate of isotropic dry etch process in all directions is identical, therefore, it is possible to sacrifice layer 202 surface certainly exposed etches to the direction of the first conductive layer 201, can etch with the direction being parallel to substrate 200 surface the sacrifice layer 202 be positioned at bottom the second conductive layer 207c simultaneously, thus form cavity 209 between the first conductive layer 207c and the first conductive layer 201.When etching sacrificial layer 202, described mask layer 203 can protect protective layer 206 surface, and when formed semiconductor devices works, prevents protective layer 206 to suffer erosion infringement; And described first connector 207c and the second connector 207b outer surface have protective layer 206 and protect, can when removing sacrifice layer 202 and semiconductor devices work time, protect described first connector 207c and the second connector 207b from damage.
In the present embodiment, the technique etching described sacrifice layer 202 is anisotropic dry etch process, and the parameter of the dry etch process of the described opposite sex comprises: etching gas comprises oxygen, and bias power is less than 100 watts, bias voltage is less than 100 volts, and temperature is greater than 100 degrees Celsius.Wherein, because the sacrifice layer 202 in the present embodiment is amorphous carbon, described oxygen can react with amorphous carbon and generate CO gas or carbon dioxide is discharged.
The first conductive layer 201 is exposed and till form through cavity 209 between the second conductive layer 207c and the first conductive layer 201 because described isotropic dry etch process proceeds to, therefore, after described isotropic dry etch process, the sacrifice layer 202 that part is not etched around described cavity 209, is still remained with; The described sacrifice layer 202 be not etched can be used in support second conductive layer 207c, protective layer 206 and mask layer 203 and is suspended on the first conductive layer 201 surface.
In the formation method of the present embodiment, form the first opening and the second opening in sacrifice layer after, on described mask layer surface, the sidewall of the first opening and the second opening and lower surface form conducting film.Wherein, be positioned at the conducting film of the first opening for the formation of the first connector, be positioned at the conducting film of the second opening for the formation of the second connector, because the first opening and the second opening are formed by etching sacrificial layer, and etch described sacrifice layer and not easily produce etch by-products, therefore not easily quality is good at the described conducting film interface that contacts with the first conductive layer, i.e. contact resistance between the contact interface of described first connector or the second connector and the first conductive layer reduces.Secondly, be positioned at the conducting film on mask layer surface for the formation of the second conductive layer, described second conductive layer is electrically connected with the first connector, because described first connector and the second conductive layer are formed by conducting film, the contact resistance therefore between described first connector and the second conductive layer is low, electrical connection properties is good.Because described first connector and the top of the second connector or the contact resistance of bottom are all reduced, the operating current of therefore formed semiconductor devices improves, thus makes the stable performance of formed semiconductor devices.
Accordingly, embodiments of the invention also provide a kind of semiconductor devices adopting said method to be formed, and please continue to refer to Fig. 7, comprising: substrate 200, first conductive layer 201 on described substrate 200 surface; Be positioned at the sacrifice layer 202 on described first conductive layer 201 surface, described sacrifice layer 202 surface has mask layer 203, has the first opening and the second opening that expose the first conductive layer 201 in described sacrifice layer 202 and mask layer 203; Be positioned at the first connector 207a of the first opening; Be positioned at the second connector 207b of the second opening, described first connector 207a and the second connector 207b and the second conductive layer 207c electricity open circuit; Be positioned at the second conductive layer 207c on mask layer 203 surface, described second conductive layer 207c is electrically connected with the first connector 207b.
In the structure of the present embodiment, in described sacrifice layer and mask layer, there is the first opening and the second opening that expose the first conductive layer, in described first opening, there is the first connector, in described second opening, there is the second connector, second conductive layer on described mask layer surface, and described second conductive layer is electrically connected with the first connector.The interface contact resistance that the bottom of described first connector and the second connector contacts with the first conductive layer is lower, and electrical connection properties between the first connector and the second conductive layer is good.Therefore described semiconductor devices operating current improve, stable performance.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a formation method for semiconductor devices, is characterized in that, comprising:
There is provided substrate, described substrate surface has the first conductive layer, and described first conductive layer surface has sacrifice layer, and described sacrificial layer surface has mask layer, and described mask layer exposes partial sacrificial layer surface;
With described mask layer for mask, etch described sacrifice layer, till exposing the first conductive layer, in sacrifice layer, form the first opening and the second opening;
On described mask layer surface, the sidewall of the first opening and the second opening and lower surface form conducting film;
The dielectric layer of filling full first opening and the second opening is formed on described conducting film surface;
After formation dielectric layer, remove the partially conductive film on mask layer surface, with graphical described conducting film, the first connector is formed in the first opening, the second connector is formed in the second opening, form the second conductive layer on mask layer surface, described second connector and the second conductive layer electricity open circuit, described second conductive layer is electrically connected with the first connector.
2. the formation method of semiconductor devices as claimed in claim 1; it is characterized in that; before formation second conductive layer, at sidewall and the lower surface formation protective layer of described sacrificial layer surface, the first opening and the second opening, described conducting film is formed at described protective layer.
3. the formation method of semiconductor devices as claimed in claim 2, it is characterized in that, the material of described protective layer is titanium nitride.
4. the formation method of semiconductor devices as claimed in claim 2, it is characterized in that, the thickness of described protective layer is 100 dust ~ 200 dusts.
5. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the material of described conducting film is titanium, tungsten, aluminium or copper.
6. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the thickness of described conducting film is 50 dust ~ 150 dusts.
7. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, the first conductive layer electricity open circuit bottom the first conductive layer bottom the second connector and the first connector.
8. the formation method of semiconductor devices as claimed in claim 7, it is characterized in that, the first conductive layer be connected with bottom the second connector is as bottom electrode, and described second conductive layer is top electrodes, and described first conductive layer, the second conductive layer, the first connector and the second connector form sensor.
9. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, described first opening and the width of the second opening parallel in substrate surface direction are 200 dust ~ 300 dusts.
10. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is different from the material of the first conductive layer, the second conductive layer and mask layer.
The formation method of 11. semiconductor devices as claimed in claim 10, is characterized in that, the material of described sacrifice layer is amorphous carbon.
The formation method of 12. semiconductor devices as claimed in claim 1, it is characterized in that, the formation method of described dielectric layer comprises: at conducting film surface deposition deielectric-coating, and described deielectric-coating fills full described second opening; Deielectric-coating described in polishing, till the conducting film exposing mask layer surface.
The formation method of 13. semiconductor devices as claimed in claim 1, is characterized in that, also comprise: after the partially conductive film removing mask layer surface, etch the mask layer exposed by described second conductive layer, till exposing sacrifice layer; After the described mask layer of etching, with the second conductive layer and mask layer for mask, adopt isotropic etching technics to etch described sacrifice layer, till exposing the first conductive layer, between described first conductive layer and the second conductive layer, form cavity.
The formation method of 14. semiconductor devices as claimed in claim 1, is characterized in that, the material of described mask layer is one or more combinations in silica, silicon nitride, silicon oxynitride.
The formation method of 15. semiconductor devices as claimed in claim 1, it is characterized in that, described substrate comprises: the insulating barrier of electric interconnection structure and semiconductor devices described in semiconductor base, the semiconductor devices being positioned at semiconductor substrate surface or semiconductor base, the electric interconnection structure being electrically connected described semiconductor devices and electric isolution.
The formation method of 16. semiconductor devices as claimed in claim 15, is characterized in that, described first conductive layer is electrically connected with described semiconductor devices by described electric interconnection structure.
The formation method of 17. semiconductor devices as claimed in claim 15, it is characterized in that, the material of described insulating barrier comprises humidity sensitive dielectric material.
18. 1 kinds adopt as any one of claim 1 to 17 method the semiconductor devices that formed, it is characterized in that, comprising:
Substrate, the first conductive layer of described substrate surface;
Be positioned at the sacrifice layer of described first conductive layer surface, described sacrificial layer surface has mask layer, has the first opening and the second opening that expose the first conductive layer in described sacrifice layer and mask layer;
Be positioned at the first connector of the first opening;
Be positioned at the second connector of the second opening, described second connector and the second conductive layer electricity open circuit;
Be positioned at second conductive layer on mask layer surface, described second conductive layer is electrically connected with the first connector.
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