CN104393952A

CN104393952A - Error correcting code decoder

Info

Publication number: CN104393952A
Application number: CN201410591500.7A
Authority: CN
Inventors: 张培
Original assignee: Suzhou Vocational University
Current assignee: Suzhou Vocational University
Priority date: 2014-10-29
Filing date: 2014-10-29
Publication date: 2015-03-04

Abstract

The invention discloses an error correcting code decoder. The error correcting code decoder comprises a generating flow from ImpulseC software to FPGA (Field Programmable Gate Array) hardware. The generating flow comprises the following steps: performing C preprocessing on an ImpulseC design file, and performing C language analysis; determining hardware and software processes in application by using a compiler at a C language analysis state; performing an initial optimizing flow, and converting corresponding loops into equivalent concurrent statements by using the compiler at a loop unrolling stage; performing secondary optimization to generate a simulation-supporting HDL (Hardware Description Language) file which describes various processes, flows and elements described in an ImpulseC source element; and generating FPGA decoder hardware. Through the way, the error correcting code decoder can be applied to the fields of digital television demodulation chips, high-speed broadband mobile communication systems, compressed image transmission, wireless local area networks and the like, is used for performing error control and detecting and correcting errors introduced in a signal transmission process, and is an important component for ensuring reliable transmission of data.

Description

A kind of Error-Correcting Code Decoders

Technical field

The present invention relates to modern digital communication systems field, particularly relate to a kind of Error-Correcting Code Decoders based on Hardware/Software Co-design Technique.

Background technology

In the error control system of Modern Communication System, except described LDPC code, common code type also has RS code, Viterbi code, convolution code, TURBO code etc.But the error-correcting performance of RS code, Viterbi code and convolution code is poor, and limit its application due to the complexity of circuit realiration.

Though the performance index of TURBO code and LDPC code are very close, but a certain distance of still having, and be not easy to hardware implementing, system complexity is higher, can not be applicable to all channels, therefore has the trend replaced by LDPC code in many cases.

For the hard-wired design of LDPC code, except the described Hardware/Software Co-design Technique based on Impulse C, directly can also adopt conventional hardware describing method, namely VHDL language designs, but when FPGA realizes, empirically need relative high input in design with instrument.

In addition, described hardware also can realize with dsp processor, but configurability is poor, and can not parallel processing, and the speed of service is by the restriction of dsp chip clock frequency.

Summary of the invention

The technical problem that the present invention mainly solves is to provide a kind of Error-Correcting Code Decoders, can be used in the fields such as Circuit in Digital Television Demodulator, high-speed wideband mobile communication system, Compressed Image Transmission, WLAN (wireless local area network), carry out error control, detecting and the mistake introduced in correction signal transmitting procedure, is the important component part ensureing reliable data transmission.

For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of Error-Correcting Code Decoders, comprising:

1), from Impulse C software to the product process of FPGA hardware:

Impulse C design document after C preliminary treatment, then carries out C language analysis; In the C language analysis phase, compiler determines the hardware and software process in application; Next carry out initial optimization flow process, in the loop unrolling stage, corresponding conversion and cycle is parallel subqueries of equal value by compiler; Again through double optimization, finally generate and can emulate hdl file, the element describing various process, stream and describe in the element of Impulse C source; Final generation FPGA decoder hardware.

2), the structure of decoder:

Decoder adopts Parallel Iteration Decoding Method structure, distributes a variable node update module (VNU), distribute a check-node update module (CNU), realize the complete parallel structure of decoder to each check-node to each variable node; After channel initialization data carry out data processing by input module feeding variable node update module, send into random asccess memory, data, through check-node update module, finally send variable node update module back to by another data wire again, complete an iteration; When condition meets or iteration completes, export iteration result by output module.

Preferably, the random asccess memory between described variable node update module and check-node update module cushions data and controls; The input and output of described input module and output module difference control data.

The invention has the beneficial effects as follows: the error correcting code that the present invention adopts is low density parity check code and LDPC code, its error correcting capability is extremely strong, and Error-floor is non-existent, as long as structure rationally, the error rate can be dropped to low arbitrarily, be a class error correcting code of approaching shannon limit at present most.

From hardware implementing angle, because LDPC code has the performance of approaching shannon limit, decoding complexity is low, and its decoding algorithm is parallel algorithm in essence, practicable parallel work-flow, reduces decoding delay, is very suitable for the parallel computation of FPGA.The present invention creates the LDPC decoding hardware algorithm achieving a Data Flow Oriented, and both occupied lower resource utilization, its throughput also can meet the needs of Practical Project, has good engineering sense.

Owing to having isolated the relation between hardware and software developing instrument and method in the past, the FPGA in software-oriented application has not embodied than the advantage of conventional processors and DSP.The present invention proposes the Hardware/Software Co-design Technique (HW/SW Co-Design) adopting latest generation based on Impulse C, can accelerate development process.Set up the mixed hardware/software application of highly-parallel, to obtain the balance of decoding rate and hardware resource consumption simultaneously.

Under Gaussian channel, achieve the design of encoder of the LDPC code of different code check in terrestrial broadcast transmission standard; Analyze the factor affecting LDPC code performance respectively, the pluses and minuses of existing channel coding schemes by BER performance analysis, for Digital Television Performance Test System provides theoretical foundation.

Accompanying drawing explanation

Fig. 1 is the optimization product process figure of Impulse C to FPGA hardware in a kind of Error-Correcting Code Decoders of the present invention;

Fig. 2 is the structured flowchart of the decoder in shown a kind of Error-Correcting Code Decoders.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described in detail, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.

Refer to Fig. 1 and Fig. 2, the embodiment of the present invention comprises:

A kind of Error-Correcting Code Decoders, comprising:

1), from Impulse C software to the product process of FPGA hardware:

3), the structure of decoder:

Decoder adopts Parallel Iteration Decoding Method structure, distributes a variable node update module (VNU), distribute a check-node update module (CNU), realize the complete parallel structure of decoder to each check-node to each variable node; After channel initialization data carry out data processing by input module feeding variable node update module, send into random asccess memory, data, through check-node update module, finally send variable node update module back to by another data wire again, complete an iteration; When condition meets or iteration completes, export random asccess memory described in iteration result between variable node update module and check-node update module by output module and data are cushioned and controls; The input and output of described input module and output module difference control data.

The present invention includes following three beneficial effects:

1, described Impulse C programmes, directly initial FPGA is become to realize from C code compilation, the time that Hardware Engineer will participate in performance conversion can be done sth. in advance to the design phase further, and simplify FPGA design process of hardware, system can design with more high efficiency software design pattern.

2, the conventional hardware describing method of identical function is contrasted, " style of stream programming " method that Streams-C compiler provides can be effectively utilized in described Impulse C storehouse, chip internal parallel decoding structure adopts pipeline organization, and reduce the use amount of logical block, hardware size is relatively little.

3, in view of China mobile television standard also adopts LDPC code, and the cell phone standby time is general shorter, existing framework is necessary for low-power consumption should be used as certain improvement, and the use amount of described coder logical block is less, hardware size is relatively little, makes power consumption obtain reduction.

The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.

Claims

1. an Error-Correcting Code Decoders, is characterized in that, comprising:

1), from Impulse C software to the product process of FPGA hardware:

Impulse C design document after C preliminary treatment, then carries out C language analysis; In the C language analysis phase, compiler determines the hardware and software process in application; Next carry out initial optimization flow process, in the loop unrolling stage, corresponding conversion and cycle is parallel subqueries of equal value by compiler; Again through double optimization, finally generate and can emulate hdl file, the element describing various process, stream and describe in the element of Impulse C source; Final generation FPGA decoder hardware;

2), the structure of decoder:

2. a kind of Error-Correcting Code Decoders according to claim 1, is characterized in that: the random asccess memory between described variable node update module and check-node update module cushions data and controls; The input and output of described input module and output module difference control data.