CN202663386U - Check node updating circuit of LDPC decoder - Google Patents
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Abstract
The utility model discloses a check node updating circuit of an LDPC (Low Density Parity Check) decoder, comprising a decomposition circuit, a subtraction circuit, a sign bit and data bit decomposition circuit, a data evaluation circuit, a sign bit processing circuit and a merging circuit. The check node updating circuit provided by the utility model is based on the LDPC codes of 1/2 code rate used in China Mobile Multimedia Broadcasting Standard; the decoding method employs a hierarchical min-sum algorithm, and a minimum value and second minimum value obtaining algorithm based on a point; and the check node updating circuit provided by the utility model is low in realization complexity, few in used hardware resources, and further capable of reducing the number of comparators without generating redundant information.
Description
Technical field
The utility model relates to low-density checksum (LDPC) decoder that is used for transfer of data error correction or error detection in the digital communication system, be particularly related to a kind of check-node refresh circuit of LDPC decoder, this check-node refresh circuit is 1/2 code check, based on minimizing and the sub-minimum algorithm of pointer, can save the quantity of comparator, and can not produce unnecessary information, be conducive to the performance of decoder.
Background technology
Chnnel coding is a very important part in the communication system, and it has guaranteed whole reliability of Communication System.Mobile communication more and more is tending towards real time high-speed transmission now, and the user is closer to the concern of data reliability in this case, therefore, realizes particularly important to algorithm research and the hardware thereof of chnnel coding with excellent in performance.Low-density checksum (Low Density Parity check, LDPC) code is one of key technology of the 4th third-generation mobile communication, the error-correcting performance of its excellence and the applications well prospect in the channel transmitting make it become the study hotspot of current field of channel coding.The LDPC code will be used widely in deep space communication, optical fiber communication, satellite digital video and audio broadcasting, magnetic/light/Hologram Storage, movement and fixed radio communication, cable modulator/demodulator and Digital Subscriber Line (DSL), and will replace gradually Turbo code.According to statistics, in the modern communications chip, 1/2 area is nearly arranged, 1/3 power consumption is on the channel coding/decoding module, the performance quality of channel decoding module will determine cost and the complexity of communication chip, also will determine the quality of digital television transmitter and receiver, and then determine the competitiveness of company on market.Therefore, design and Implement a high-performance, low area and more the LDPC decoder of low-power consumption be significant.
The LDPC code is the special linear block codes of a class, and special character just is that the number of nonzero element in its parity check matrix H is far smaller than the number of neutral element, so the LDPC code can define according to check matrix.Simultaneously, the LDPC code can represent with bipartite graph, is called Tanner figure, and each Tanner figure and corresponding check matrix are directly corresponding, and code word corresponding to test matrix row be called variable node, and the capable corresponding code word of test matrix is called the check node.
Traditional decoding algorithm is put letter and is transmitted decoding algorithm (being also referred to as sum-product algorithm), is a kind of Parallel Decoding Algorithm that repeatedly transmits based on check-node on the bipartite graph and variable node information.When decoder receives a code word, can obtain the reliability information of each bit node, calculate the reliability standard of the check-node that links to each other with variable node according to the authentic communication of these variable nodes.Simultaneously according to the reliability information of check-node, upgrade the reliability information of variable node, the authentic communication between this two category node of so iterating just can translate correct code word.
In order to utilize as early as possible the information of the variable node that had upgraded, accelerate the convergent iterations speed of code word, hierarchical algorithm has been proposed.In iteration, in having upgraded the H matrix, behind the check information of certain delegation's nonzero element, upgrade the variable information of all nonzero elements of each nonzero element respective column at once, and then the next line of H matrix is deciphered.Can use in advance the variable node information of having upgraded, convergence speedup speed like this.In iterative decoding, only need half iterations of sum-product algorithm.
On the other hand, theoretical according to Density evolution, people have proposed the correction minimum-sum algorithm on the basis of minimum-sum algorithm.Revising minimum-sum algorithm is to multiply by a modifying factor α (0＜α＜1) in the information to check-node.With hierarchical algorithm with revise minimum-sum algorithm and combine, namely simplify the renewal of check-node with the correction minimum-sum algorithm on the basis of hierarchical algorithm, the complexity that reduces to decipher.This algorithm is called layered revised min-sum algorithm.
Hardware based on the LDPC decoder of China Mobile multimedia broadcasting (CMMB) standard is realized, can adopt layered revised min-sum algorithm; Wherein, check-node update module CNU is the main part of decoder computing path, also is the core, and its main task is to finish renewal and the computing of the log-likelihood information of check-node.Usually, traditional check-node update module circuit can use too much hardware resource, therefore increases the complexity of circuit realization and the power consumption of whole decoder, and this becomes existing LDPC decoder Shortcomings part.
The utility model content
The shortcoming and deficiency that exist in order to overcome prior art, the utility model provides a kind of check-node refresh circuit of LDPC decoder, the utility model is based on the LDPC code of 1/2 code check that uses in the China Mobile multimedia broadcasting standard, interpretation method adopts layered min-sum algorithm, and wherein the modifying factor value is 0.75, and the decoding maximum iteration time is 10 times, in iterative process, the posterior information of variable node expands to 6 bit bit wides, 1 bit sign position wherein, and 5 is data bit; Check-node information adopts 4 bit bit wides, and wherein 1 is sign bit, and 3 is data bit, and the utility model mainly is that the circuit for the log-likelihood information of check-node upgrades.
The utility model adopts following technical scheme
A kind of check-node refresh circuit of LDPC decoder comprises
Decomposition circuit: with the information decomposition of the check-node that receives,
Subtraction circuit: the information data that decomposition circuit is obtained with subtract each other the output data from the nodal information in the nodal information memory, and the data of output are carried out Overflow handling,
Sign bit and data bit decomposition circuit: the data that subtraction circuit obtains are carried out sign bit and data bit decomposition, and the data bit information of output is taken absolute value,
The data evaluation circuit: from the absolute value of data bit information, draw minimum value and sub-minimum, and provide the index information of minimum value,
The sign bit treatment circuit: if the sign bit data of input is identical, output symbol invariant position then, otherwise the respectively negate output of incoming symbol position,
Consolidation circuit: data evaluation circuit output data and sign bit treatment circuit output data are merged the check-node after obtaining upgrading.
Described decomposition circuit, subtraction circuit, sign bit are connected with consolidation circuit and are connected with data bit decomposition circuit, data evaluation circuit, sign bit treatment circuit.
Described data evaluation circuit comprises the first comparison gate, second relatively gate, the 3rd comparison gate, the first pseudo-arrangement machine, the second pseudo-arrangement machine, and 2 select 1 gate and 1 index information circuit; The described first the first output, the second output that compares gate is connected with first input end, second input of the first pseudo-arrangement machine respectively;
The second the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the first pseudo-arrangement machine respectively;
The 3rd the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the second pseudo-arrangement machine respectively;
The first output of the first pseudo-arrangement machine, the second output are connected with first input end, second input of the second pseudo-arrangement machine respectively;
2 select the input of 1 gate to be connected with the first comparison output, the second comparison output that compares gate that compares gate respectively; The index output and 2 of the first pseudo-arrangement machine selects the selection signal end of 1 gate to be connected;
2 select output, the index output of the first pseudo-arrangement machine, the 3rd comparison output that compares gate of 1 gate to be connected with the input of index information circuit respectively.
The index output of the second pseudo-arrangement machine is connected with the selection input of index information circuit; The four-input terminal ground connection of index information circuit.
Described sign bit treatment circuit is the XOR gate array that is made of XOR gate.
Described pseudo-arrangement machine comprises the first comparator, the second comparator, and first compares gate and 3 selects 1 gate;
The first input end of described pseudo-arrangement machine and the second comparator and first relatively gate first input end be connected, the second input selects the input of 1 gate to be connected with the first input end and 3 of the first comparator, the 3rd input is connected with the first the second input that compares gate with the first comparator, and four-input terminal selects the input of 1 gate to be connected with second input and 3 of the second comparator;
The output of the output of described the first comparator, the second comparator and the first relatively comparison output of gate selects the selection signal end of 1 gate to be connected with 3 respectively;
The first the first output and 3 that compares gate selects the input of 1 gate to be connected; The described first output that compares gate is comparison output, the first output and the second output from top to bottom successively.
A kind of check-node update method of LDPC decoder comprises the steps:
(1) the check-node rin of 15 bit bit wides of verification nodal information memory is decomposed into the information data of 66 bit bit wides, be respectively rin0, rin1, rin2, rin3, rin4, rin5, the principle of wherein decomposing is to have comprised the check-node rin reduction of 15 bit bit wides of last check-node lastest imformation; Further, for check-node rin, rin[5:0] represent successively the sign bit of rin5 ~ rin0, rin[8:6] represent the index of minimum value among rin0 ~ rin5, rin[11:9] represent the numerical value of sub-minimum among rin0 ~ rin5, rin[14:12] represent the numerical value of minimum value among rin0 ~ rin5.
The information node of 66 bit bit wides subtracts each other the output data that obtain 66 bit bit wides in the information data of (2) 66 bit bit wides and the information node memory, and these are carried out Overflow handling; Rin0, rin1, rin2, rin3, rin4, rin5 are subtracted each other with information node din0, din1, din2, din3, din4, din5 from 66 bit bit wides of information node memory respectively, export the output data of 66 bit bit wides, respectively sum0_ov, sum1_ov, sum2_ov, sum3_ov, sum4_ov, sum5_ov, and they are carried out data from overflow process, obtain sum0, sum1, sum2, sum3, sum4, sum5.Wherein, the judgment principle that data from overflow is processed is as follows: if positive number Reduction of Students' Study Load number, and subtract each other the result so that highest order is 1, and just be and overflow, then the result is set to 011111; If negative subtracts positive number, and subtract each other the result so that highest order is 0, then overflow for negative, then the result is set to 100001.
(3) data behind the Overflow handling are carried out sign bit and data bit decomposition, obtain the data bit information of 65 bit bit wides, the sign bit information of 61 bit bit wides, and the data bit information that obtains is asked absolute value; Be specially: the data bit information that obtains 65 bit bit wides after the decomposition, respectively sum0[4:0], sum1[4:0], sum2[4:0], sum3[4:0], sum4[4:0], sum5[4:0], the sign bit information sum0[5 of 61 bit bit wides], sum1[5], sum2[5], sum3[5], sum4[5], sum5[5].And data bit information taken absolute value, obtain the data of 65 bit bit wides, be respectively di0, di1, di2, di3, di4, di5.
(4) data bit information and sign bit information are carried out respectively data evaluation and sign bit processing computing; The data evaluation is realized obtaining minimum value and sub-minimum from 6 data by the data evaluation circuit, gets low three numerical value, and the result is respectively minimum value m1 and sub-minimum m2, and provides the index information index of minimum value, and three outputs all are 3 bit bit wides.It is that data are judged by the sign bit treatment circuit to symbol that sign bit is processed computing, if it is identical to input 6 sign bit data, and output symbol invariant position then; If it is different to input 6 sign bit data, then respectively negate of output symbol position.
(5) result that the result who the data evaluation is exported and sign bit processing computing obtain merges the check-node that forms after upgrading.
Minimum value m1, the sub-minimum m2 of 3 bit bit wides of data evaluation circuit output, index information index and by sign bit sign0, sign1, sign2, sign3, sign4, the sign5 of 61 bit bit wides of sign bit treatment circuit output, through consolidation circuit, form the check-node rout after upgrading, it is 15 bit bit wides.Wherein, the principle that data bit and sign bit are merged is: with m1[2:0], m1[2:0] and index[2:0] respectively as rout[14:12], rout[11:9] and rout[8:6], sign5 ~ sign0 is then successively as rout[5:0].
The beneficial effects of the utility model:
The implementation complexity of circuit is low, and the hardware resource of use is few, and the while minimizes and the sub-minimum algorithm based on pointer, can save the quantity of comparator, and can not produce unnecessary information, is conducive to the performance of decoder.
Description of drawings
Fig. 1 is the flow chart of the check-node refresh circuit of a kind of LDPC decoder of the utility model;
Fig. 2 is the structure chart of data evaluation circuit in the utility model;
Fig. 3 is the structure chart of pseudo-arrangement machine among Fig. 2.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, but execution mode of the present utility model is not limited to this.
Embodiment
Be illustrated in figure 1 as the flow chart of the utility model check-node refresh circuit:
A kind of check-node update method of LDPC decoder comprises the steps:
(1) the check-node rin of 15 bit bit wides of verification nodal information memory is decomposed into the information data of 66 bit bit wides, be respectively rin0, rin1, rin2, rin3, rin4, rin5, the principle of wherein decomposing is to have comprised the check-node rin reduction of 15 bit bit wides of last check-node lastest imformation; For check-node rin, rin[5:0] represent successively the sign bit of rin5 ~ rin0, rin[8:6] represent the index of minimum value among rin0 ~ rin5, rin[11:9] represent the numerical value of sub-minimum among rin0 ~ rin5, rin[14:12] represent the numerical value of minimum value among rin0 ~ rin5.
The information node of 66 bit bit wides subtracts each other the output data that obtain 66 bit bit wides in the information data of (2) 66 bit bit wides and the information node memory, and these are carried out Overflow handling; Rin0, rin1, rin2, rin3, rin4, rin5 are subtracted each other with information node din0, din1, din2, din3, din4, din5 from 66 bit bit wides of information node memory respectively, export the output data of 66 bit bit wides, respectively sum0_ov, sum1_ov, sum2_ov, sum3_ov, sum4_ov, sum5_ov, and they are carried out data from overflow process, obtain sum0, sum1, sum2, sum3, sum4, sum5.Wherein, the judgment principle that data from overflow is processed is as follows: if positive number Reduction of Students' Study Load number, and subtract each other the result so that highest order is 1, and just be and overflow, then the result is set to 011111; If negative subtracts positive number, and subtract each other the result so that highest order is 0, then overflow for negative, then the result is set to 100001.
(3) data behind the Overflow handling are carried out sign bit and data bit decomposition, obtain the data bit information of 65 bit bit wides, the sign bit information of 61 bit bit wides, and the data bit information that obtains is asked absolute value; Be specially: the data bit information that obtains 65 bit bit wides after the decomposition, respectively sum0[4:0], sum1[4:0], sum2[4:0], sum3[4:0], sum4[4:0], sum5[4:0], the sign bit information sum0[5 of 61 bit bit wides], sum1[5], sum2[5], sum3[5], sum4[5], sum5[5].And data bit information taken absolute value, obtain the data of 65 bit bit wides, be respectively di0, di1, di2, di3, di4, di5.
(4) data bit information and sign bit information are carried out respectively data evaluation and sign bit processing computing; The data evaluation is realized obtaining minimum value and sub-minimum from 6 data by the data evaluation circuit, gets low three numerical value, and the result is respectively minimum value m1 and sub-minimum m2, and provides the index information index of minimum value, and three outputs all are 3 bit bit wides.It is that data are judged by the sign bit treatment circuit to symbol that sign bit is processed computing, if it is identical to input 6 sign bit data, and output symbol invariant position then; If it is different to input 6 sign bit data, then respectively negate of output symbol position.
(5) result that the result who the data evaluation circuit is exported and sign bit processing computing obtain merges the check-node that forms after upgrading.
Minimum value m1, the sub-minimum m2 of 3 bit bit wides of data evaluation circuit output, index information index and by sign bit sign0, sign1, sign2, sign3, sign4, the sign5 of 61 bit bit wides of sign bit treatment circuit output, through consolidation circuit, form the check-node rout after upgrading, it is 15 bit bit wides.Wherein, the principle that data bit and sign bit are merged is: with m1[2:0], m1[2:0] and index[2:0] respectively as rout[14:12], rout[11:9] and rout[8:6], sign5 ~ sign0 is then successively as rout[5:0].
A kind of check-node refresh circuit of LDPC decoder comprises
Decomposition circuit: with the information decomposition of the check-node that receives,
Subtraction circuit: the information data that decomposition circuit is obtained with subtract each other the output data from the nodal information in the nodal information memory, and the data of output are carried out Overflow handling,
Sign bit and data bit decomposition circuit: the data that subtraction circuit obtains are carried out sign bit and data bit decomposition, and the data bit information of output is taken absolute value,
The data evaluation circuit: from the absolute value of data bit information, draw minimum value and sub-minimum, and provide the index information of minimum value,
The sign bit treatment circuit: if the sign bit data of input is identical, output symbol invariant position then, otherwise the respectively negate output of incoming symbol position,
Consolidation circuit: data evaluation circuit output data and sign bit treatment circuit are merged the check-node after obtaining upgrading.
As shown in Figure 2: the data evaluation circuit is the nucleus module of whole check-node refresh circuit, the function that it is realized is obtained minimum value m1 and sub-minimum m2 from the data of 66 bit bit wides, get low three numerical value, and provide the index information index of minimum value m1, three outputs all are 3 bit widths.
Described data evaluation circuit comprises the first comparison gate, second relatively gate, the 3rd comparison gate, the first pseudo-arrangement machine, the second pseudo-arrangement machine, and 2 select 1 gate and 1 index information circuit; The described first the first output, the second output that compares gate is connected with first input end, second input of the first pseudo-arrangement machine respectively;
The second the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the first pseudo-arrangement machine respectively;
The 3rd the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the second pseudo-arrangement machine respectively;
The first output of the first pseudo-arrangement machine, the second output are connected with first input end, second input of the second pseudo-arrangement machine respectively;
2 select the input of 1 gate to be connected with the first comparison output, the second comparison output that compares gate that compares gate respectively; The index output and 2 of the first pseudo-arrangement machine selects the selection signal end of 1 gate to be connected;
2 select output, the index output of the first pseudo-arrangement machine, the 3rd comparison output that compares gate of 1 gate to be connected with the input of index information circuit respectively, and the index output of the second pseudo-arrangement machine is connected with the selection input of index information circuit; The four-input terminal ground connection of index information circuit.
The index information circuit is exported low two of index information, is respectively Index[0] and Index[1], the indexed results of the second pseudo-arrangement machine then is the highest order Index[2 of final index information].
Relatively the function of gate realization is: two input data are compared, first is output as larger data in two numbers, second is output as less data in two numbers, comparative result then exports 1 or 0,1 expression the first input data are greater than the second input data, and 0 expression the first input data are less than or equal to the second input data;
The function that pseudo-arrangement machine is realized is: select minimum value and sub-minimum from 4 input data, the first output is sub-minimum m2, the second output is minimum value m1, simultaneously, output indexed results Index, indexed results Index is that high level 1 expression second is inputted greater than the 4th input, and indexed results Index is that low level 0 expression the second input Data2 is less than or equal to the 4th input Data4;
Data di0, di1, di2, di3, di4, di5 for 65 bit widths, wherein di0, di1 are input to the first comparison gate, di2, di3 are input to second and compare gate, di4, di5 are input to the 3rd and compare gate, the first output of the second pseudo-arrangement machine is the sub-minimum m2 of this data evaluation circuit, and the second output of the second pseudo-arrangement machine is minimum value m1; The index information circuit is exported low two of final index information, is respectively Index[0] and Index[1], the indexed results of the second pseudo-arrangement machine then is the highest order Index[2 of final index information].
As shown in Figure 3: described pseudo-arrangement machine comprises the first comparator, the second comparator, and first compares gate and 3 selects 1 gate;
The first input end Data1 of described pseudo-arrangement machine and the second comparator and first relatively gate first input end be connected, the second input Data2 selects the input of 1 gate to be connected with the first input end and 3 of the first comparator, the 3rd input Data3 is connected with the first the second input that compares gate with the first comparator, and four-input terminal Data4 selects the input of 1 gate to be connected with second input and 3 of the second comparator;
The output of the output of described the first comparator, the second comparator and the first relatively comparison output of gate selects the selection signal end of 1 gate to be connected with 3 respectively;
The first the first output and 3 that compares gate selects the input of 1 gate to be connected;
Described first compares the indexed results Index that gate is exported pseudo-arrangement machine, the first output output1; 3 select 1 gate to export the second output output2.
Above-described embodiment is the better execution mode of the utility model, but execution mode of the present utility model is not limited by the examples, other any do not deviate from change, the modification done under Spirit Essence of the present utility model and the principle, substitutes, combination, simplify, all should be the substitute mode of equivalence, be included in the scope of the present utility model.
Claims (4)
1. the check-node refresh circuit of a LDPC decoder, it is characterized in that, comprise decomposition circuit, subtraction circuit, sign bit and data bit decomposition circuit, data evaluation circuit, sign bit treatment circuit and consolidation circuit, described decomposition circuit, subtraction circuit, sign bit are connected with consolidation circuit and are connected with data bit decomposition circuit, data evaluation circuit, sign bit treatment circuit.
2. refresh circuit according to claim 1, it is characterized in that described data evaluation circuit comprises the first comparison gate, second relatively gate, the 3rd comparison gate, the first pseudo-arrangement machine, the second pseudo-arrangement machine, 2 select 1 gate and 1 index information circuit; It is respectively comparison output, the first output, the second output that described relatively gate has three outputs;
The described first the first output, the second output that compares gate is connected with first input end, second input of the first pseudo-arrangement machine respectively;
The second the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the first pseudo-arrangement machine respectively;
The 3rd the first output, the second output that compares gate is connected with the 3rd input, the four-input terminal of the second pseudo-arrangement machine respectively;
The first output of the first pseudo-arrangement machine, the second output are connected with first input end, second input of the second pseudo-arrangement machine respectively;
2 select the input of 1 gate to be connected with the first comparison output, the second comparison output that compares gate that compares gate respectively; The index output and 2 of the first pseudo-arrangement machine selects the selection signal end of 1 gate to be connected;
2 select output, the index output of the first pseudo-arrangement machine, the 3rd comparison output that compares gate of 1 gate to be connected with the input of index information circuit respectively;
The index output of the second pseudo-arrangement machine is connected with the selection input of index information circuit; The four-input terminal ground connection of index information circuit.
3. refresh circuit according to claim 1 is characterized in that described sign bit treatment circuit is the XOR gate array that is made of XOR gate.
4. refresh circuit according to claim 2 is characterized in that described pseudo-arrangement machine comprises the first comparator, the second comparator, and first compares gate and 3 selects 1 gate;
The first input end of described pseudo-arrangement machine and the second comparator and first relatively gate first input end be connected, the second input selects the input of 1 gate to be connected with the first input end and 3 of the first comparator, the 3rd input is connected with the first the second input that compares gate with the first comparator, and four-input terminal selects the input of 1 gate to be connected with second input and 3 of the second comparator;
The output of the output of described the first comparator, the second comparator and the first relatively comparison output of gate selects the selection signal end of 1 gate to be connected with 3 respectively;
The first the first output and 3 that compares gate selects the input of 1 gate to be connected.
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| CN109245775B (en) * | 2017-07-10 | 2022-08-09 | 深圳市中兴微电子技术有限公司 | Decoder and method for realizing decoding |
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