CN104112794A - Manufacturing method for selective emitter solar battery - Google Patents
Manufacturing method for selective emitter solar battery Download PDFInfo
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- CN104112794A CN104112794A CN201410360132.5A CN201410360132A CN104112794A CN 104112794 A CN104112794 A CN 104112794A CN 201410360132 A CN201410360132 A CN 201410360132A CN 104112794 A CN104112794 A CN 104112794A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000005245 sintering Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000009830 intercalation Methods 0.000 claims description 20
- 230000002687 intercalation Effects 0.000 claims description 20
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 13
- 238000002360 preparation method Methods 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 230000003667 anti-reflective effect Effects 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- CLVOYFRAZKMSPF-UHFFFAOYSA-N n,n-dibutyl-4-chlorobenzenesulfonamide Chemical compound CCCCN(CCCC)S(=O)(=O)C1=CC=C(Cl)C=C1 CLVOYFRAZKMSPF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000001816 cooling Methods 0.000 abstract description 4
- 238000011049 filling Methods 0.000 abstract description 4
- 230000031700 light absorption Effects 0.000 abstract description 4
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a manufacturing method for a selective emitter solar battery. The manufacturing method for the selective emitter solar battery includes that removing a damaged layer, diffusing in two steps, etching a positive electrode groove, sintering positive electrode filling, etching reversely to form a highly doped region and a lightly doped region, wherein the positive electrode comprises a side wall electrode plate, an embedded electrode plate which extends in a broken-line mode, and a main electrode strip, the two-step diffusion comprises constant-temperature primary diffusion and cooling diffusion, and the cooling diffusion time is 1.5 to 2 times of the primary diffusion time. The selective emitter solar battery manufactured by the method enables the whole light absorption efficiency and photon-generated carrier gathering efficiency to be improved, avoids the dead layer phenomenon at the surface, is capable of simultaneously regulating the short-circuit current and open-circuit voltage and enables the battery filling rate to be improved.
Description
Technical field
The present invention relates to a kind of method for manufacturing solar battery, especially relate to a kind of manufacture method of selective emitter solar battery.
Background technology
Solar battery technology is the New Energy Industry of tool potentiality and realistic meaning, is subject to the very big support of national governments, and the research and development of its manufacturing technology also have meaning;
For routine, produce with for solar cell, go for higher short-circuit current density, need to obtain light dope concentration and more shallow joint dark; And to obtain higher open circuit voltage, need higher surface doping concentration.Meanwhile, higher doping content is conducive to obtain good ohmic contact, reduces the series resistance of battery.Selective emitter solar battery structure is balance above-mentioned requirements preferably, conventionally the method for preparing selective emitter solar battery comprises anti-erosion method, mask corrosion method, bury grid method etc., but there is photo-generated carrier collection efficiency and the low problem of efficiency of light absorption in conventional method in the past, even tend to occur because surface concentration is too high, occurring the phenomenon of " dead layer ", cause increasing of series resistance, reduced the filling rate of battery.
Summary of the invention
The invention provides a kind of manufacture method of selective emitter solar battery, the selective emitter solar battery that uses the present invention to prepare can improve efficiency of light absorption on the whole, photo-generated carrier collection efficiency, avoid surperficial dead layer phenomenon, can regulate short circuit current and open circuit voltage, to improve battery filling rate simultaneously;
Preparation method of the present invention comprises step:
(1) provide the monocrystalline silicon piece of the first conduction type, NaOH solution damages layer to described monocrystalline silicon piece and removes, and subsequently described monocrystalline silicon piece is carried out to washed with de-ionized water and drying and processing;
(2) diffusion technology is carried out in the front of described monocrystalline silicon piece, form the second conduction type doped region, described doped region junction depth is 0.5-1.5um;
(3) anti-etching technique, forms high-doped zone and doped regions;
(4) deposition anti-reflective film;
Described diffusion technology is two step diffusions, and comprises: with nitrogen, for taking phosphorus gas, phosphorus oxychloride is phosphorus source, carries out constant temperature and tentatively spread within the scope of 950-1050 degree celsius temperature; With constant speed, cool to final temperature afterwards, advance diffusion simultaneously, when temperature arrives final temperature, stop logical phosphorus source;
Further, summation diffusion time of described preliminary diffusion and propelling diffusion is 25 minutes, and stopping diffusion temperature is 750 degrees Celsius, and the time of propelling diffusion is 1.5-2 times of preliminary diffusion time;
Further between step and step, also comprise that front electrode forms step, described front electrode forms step and comprises: the front-side etch in described monocrystalline silicon piece doped region forms front electrode channel patterns, and the degree of depth of described front electrode groove is described junction depth 1/4th to 1/2nd; And fill silver paste in the groove of this front electrode channel patterns;
Further, described anti-reflective film is double-decker, and wherein more close light-struck upper strata refractive index is greater than lower floor;
Further, in the groove of front electrode channel patterns, fill silver paste and carry out sintering processes afterwards to form front electrode;
Further, described front electrode channel patterns comprises: a plurality of side-wall electrode sheet grooves pair that are parallel to each other, each side-wall electrode sheet groove is to having two side-wall electrode sheet grooves that are parallel to each other, side-wall electrode sheet groove extends to opposite side by a side of front side of silicon wafer, a plurality of side-wall electrode sheet grooves between distance be greater than the distance between side-wall electrode sheet groove centering side-wall electrode sheet groove;
Further, described side-wall electrode sheet groove between distance be described side-wall electrode sheet groove to described in 2 times of distance between side-wall electrode sheet groove;
Further, between the described side-wall electrode sheet groove of described a plurality of side-wall electrode sheet groove centerings, also there is the intercalation electrode sheet groove extending along broken line mode, this intercalation electrode sheet groove is communicated with described side-wall electrode sheet groove at knuckle place, and described many main electrode bar grooves are through this knuckle place; Corresponding, after described sintering processes, the silver paste in described side-wall electrode sheet groove, main electrode bar groove and intercalation electrode sheet groove forms respectively side-wall electrode sheet, main electrode bar and the intercalation electrode sheet in front electrode;
Further, described anti-etching technique comprises: at front side of silicon wafer, use anti-etching mask pattern coated electrode region, described electrode zone refers to: the region between two side-wall electrode sheets of the side-wall electrode sheet of a plurality of side-wall electrode sheet centerings and side-wall electrode centering, and main electrode bar region; Dry etching is carried out in front side of silicon wafer region to the doping not covered by anti-etching mask pattern, and etch depth is identical with the degree of depth of front electrode, etches into the position parallel with front electrode bottom always; Clean, remove anti-resistant layer, so far by described doped region, formed heavily doped region and doped regions, completed the preparation of selective emitting electrode structure;
Wherein said side-wall electrode sheet is to referring to the combination that has comprised two side-wall electrode sheets internally being formed by side-wall electrode sheet groove;
Accompanying drawing explanation
Silicon chip schematic diagram after Fig. 1 diffusing, doping;
Fig. 2 (a)-2(c) doping content is with the distribution of the degree of depth;
Fig. 3 front side of silicon wafer electrode trenches pattern schematic diagram;
In Fig. 4 Fig. 3 along the profile of A-B direction;
The selective emitting electrode structure (not showing anti-reflecting layer) forming after the anti-etching technique of Fig. 5;
In Fig. 6 Fig. 5 along the profile of A-B direction.
Embodiment
In order to make object of the present invention and beneficial effect and advantage become more directly perceived and remove, below with reference to embodiment and accompanying drawing, next the present invention will be further described in detail.Should be appreciated that specific embodiment provided herein is only to understand the present invention, can not limit the present invention;
" A layer is on B layer " using in specification is interpreted as B layer on position relationship and is positioned at the more upper strata of A layer, but can not get rid of, also has extra layer between A layer and B layer;
First the more complicated execution mode of take is example, the present invention is made a detailed explanation, but clearly this embodiment is only the enforceable aspect of the present invention, and it does not represent full content of the present invention, can not be used for limiting practical range of the present invention;
Please refer to Fig. 1-5, first, select for example boron of (111) face to adulterate p type single crystal silicon sheet (1) as semiconductor substrate, adopt the NaOH solution that concentration is 15% to damage layer removal to this monocrystalline silicon piece, subsequently this monocrystalline silicon piece (1) is carried out to washed with de-ionized water and drying and processing, the monocrystalline silicon piece before being spread (1);
Then silicon chip (1) is sent into stopped pipe high temperature dispersing furnace carries out two step diffusion technologys to front side of silicon wafer (S1), and with nitrogen, for taking phosphorus gas, phosphorus oxychloride is phosphorus source, carries out just diffusion within the scope of 950-1050 degree celsius temperature, and be 20 minutes diffusion time; The speed cooling with 20 degrees celsius/minute by temperature afterwards advances diffusion simultaneously; Until temperature, be down to after 750-850 degree Celsius, stop logical phosphorus oxychloride; Insulation, completes heavy doping, forms doped region (2), and the junction depth (d1) of this doped region (2) is within the scope of 0.5-1.5um, and doping content self-assembling formation is for to be reduced gradually to silicon chip inside by front face surface.At this, to compare with the heavy doping technique of a traditional step constant temperature diffusion, this two steps diffusion technology can regulate the concentration gradient of doping content from silicon chip surface to silicon chip inside, and this plays an important role the balance between balance short circuit current and open circuit voltage;
Total time for the adjustable two step diffusions of two above-mentioned step diffusion technologys spreads and advances the ratio of diffusion time to obtain different doping concentration distributions from preliminary, in technique, the distribution of doping content to the life-span of charge carrier to very responsive, gentle doping content gradient is conducive to improve the life-span of charge carrier, can occasionally effectively reduce the series resistance of battery, balance short circuit current can open circuit voltage;
Fig. 2 (a)-2(c) shown that 950-1050 degree Celsius for preliminary diffusion temperature, 750 degrees Celsius for advancing the final temperatures of diffusion temperature, Zong diffusion time be the doping content of 25 minutes with the distribution of the degree of depth, data are to record according to spreading resistance (SPR) method.The described degree of depth refers to from the distance on front side of silicon wafer surface.Preliminary diffusion adopts constant temperature diffusion, advances diffusion to adopt uniform decrease in temperature diffusion, with constant rate of temperature fall, cools to final temperature, and temperature reaches final temperature and stops logical phosphorus source.What Fig. 2 (a) described is to be preliminary diffusion time 15 minutes, propelling is diffused as the situation of 10 minutes, what Fig. 2 (b) described is to be preliminary diffusion time 10 minutes, propelling is diffused as the situation of 15 minutes, what Fig. 2 (b) described is to be preliminary diffusion time 8 minutes, advances the situation that is diffused as 17 minutes.The distribution of doping content is degree Celsius insensitive to preliminary diffusion, the distribution of doping content is responsive with the ratio of preliminary diffusion time to advancing diffusion time, when advancing diffusion time and tentatively the ratio between diffusion time is greater than 1.5, with reference to figure 2(b) situation about describing, can reach optimal doping concentration distribution; For example, but excessive ratio also can cause doping content too even, and the efficiency of battery is had a negative impact on the contrary, can reduce significantly short circuit current, preferably advance the ratio between diffusion time and preliminary diffusion time to be less than 2;
Cooling is come out of the stove, and uses conventional photoetching-etch process, in the front of silicon chip doped region (2) (S1) etching, forms front electrode channel patterns, and this front electrode channel patterns is consistent with the final whole positions of electrode that form, with reference to figure 2, this electrode trenches pattern has a plurality of side-wall electrode sheet grooves of being parallel to each other to (41), each side-wall electrode sheet groove has two side-wall electrode sheet grooves (411) that are parallel to each other to (41), side-wall electrode sheet groove (411) extends to opposite side by a side of front side of silicon wafer (S1), a plurality of side-wall electrode sheet grooves are greater than side-wall electrode sheet groove to the distance (d22) between side-wall electrode sheet groove (411) in (41) to the distance between (41) (d21), being preferably side-wall electrode sheet groove is side-wall electrode sheet groove in (41) between side-wall electrode sheet groove (411) 2 times of distance to the distance between (41), a plurality of main electrode bar grooves (5), extend along the direction intersecting with side-wall electrode sheet groove (411), are preferably vertical with side-wall electrode sheet groove (411), between the plurality of side-wall electrode sheet groove is to the side-wall electrode sheet groove (411) in (41), also there is the intercalation electrode sheet groove (42) extending along broken line mode, this intercalation electrode sheet groove (42) is communicated with side-wall electrode sheet groove (411) at knuckle place, and these many main electrode bar grooves (5) are through this knuckle place, and main electrode bar groove (5) is communicated with the place that side-wall electrode sheet groove (411) intersects at main electrode bar groove (5) with side-wall electrode sheet groove (411), the degree of depth of this side-wall electrode sheet groove (411), main electrode bar groove (5) and intercalation electrode groove (42) is junction depth between 1/4th to 1/2nd,
Front electrode is filled, to side-wall electrode sheet groove (411), in main electrode bar groove (5) and intercalation electrode sheet groove (42), fill silver paste, and by silk-screen printing technique, form back electrode at silicon chip back side, through sintering, form front electrode and backplate (6); Corresponding, the silver paste in side-wall electrode sheet groove (411), main electrode bar groove (5) and intercalation electrode sheet groove (42) forms respectively side-wall electrode sheet (411E), main electrode bar (5E) and the intercalation electrode sheet (42E) in front electrode.Therefore, the place contact that main electrode bar (5E) intersects at it with side-wall electrode sheet (411E) is connected, at intercalation electrode sheet (42E) knuckle place, contact is connected intercalation electrode sheet (42E) with side-wall electrode sheet (411E), and main electrode bar (5) is through this intercalation electrode sheet (42E) knuckle place;
Anti-etching technique, in the anti-etching mask pattern coated electrode of front side of silicon wafer region, this resistant layer pattern can be realized by photoetching-masking process of knowing, this electrode zone refers to: a plurality of side-wall electrode sheets are to the side-wall electrode sheet (411E) in (41E) (side-wall electrode sheet is herein to referring to the combination that has comprised two side-wall electrode sheets internally being formed by side-wall electrode sheet groove) and the region between two side-wall electrode sheets (411E) of side-wall electrode centering, and main electrode bar (5E) region, i.e. non-C region in Fig. 2; Front side of silicon wafer region C to the doping not covered by anti-etching mask pattern carries out dry etching, etch depth is identical with the degree of depth (d3) of front electrode, etch into the position parallel with front electrode (comprising side-wall electrode sheet (411E), main electrode bar (5E) and intercalation electrode sheet (42E)) bottom always; Clean, remove anti-resistant layer, so far by doped region (2), formed heavily doped region (21) and doped regions (22), completed the preparation of selective emitting electrode structure;
It should be noted that, this intercalation electrode sheet (42E) extending along broken line not only can be collected in heavily doped region and along side-wall electrode sheet (411E) vertical direction, to migrate mobile photo-generated carrier and also can collect along side-wall electrode sheet (411E) parallel direction and migrate mobile photo-generated carrier;
In addition, with reference to figure 4, side-wall electrode sheet (411E) and intercalation electrode sheet (42) upper surface deposition anti-reflective film (7) at the doped regions (21) forming and heavily doped region (22) and front electrode, the sidewall of side-wall electrode sheet (411E) does not deposit anti-reflective film (7), this be because cover side-wall electrode layer (411E) on the sidewall of heavily doped region (22) thus sidewall be conducive to reflection and be irradiated at a certain angle active region that the sunlight on electrode layer is irradiated to battery to improve efficiency of light absorption; The material of anti-reflecting layer can be silicon nitride, silica, titanium dioxide, and can be set to double-decker, wherein more close light-struck upper strata (71) refractive index is greater than lower floor (72), the benefit of doing is like this for example can effectively utilize, with wide-angle very (more than 60 degree) to incide the light that solar-electricity aurora are shown up, and the light that incides first surface can be locked in high refractive index layer and be difficult for reflecting.The double-decker that for example can use identical material but have different refractivity, as anti-reflective film, also can be used different materials as double-deck anti-reflective film;
In addition, after carrying out diffusion technology, carry out plasma etch process to remove edge PN junction;
In addition, due to the side wall construction of side-wall electrode sheet (411E), it doesn't matter with the width of main electrode bar (5E) (be parallel to front side of silicon wafer and perpendicular to the distance on main electrode bar bearing of trend) for the contact area of side-wall electrode sheet (411E) and main electrode bar (5E).Therefore in the situation that not reducing carrier collection efficiency, the ratio routine that the width of main electrode bar (5E) can be done narrower, for example the height of main electrode bar (5E) can be greater than the width of main electrode bar, and the width of preferred main electrode bar is 1/4th to 1/8th of main electrode bar height.The advantage of so doing is that the electrode coverage that reduces battery sensitive surface amasss, and increases illuminating area;
To the understanding of the present invention of above record, should stand in those skilled in the art's angle, to the obvious distortion of above invention and factor substitute and the technical scheme forming all within protection scope of the present invention.
Claims (8)
1. a preparation method of solar battery, comprises the following steps:
(1) provide the monocrystalline silicon piece of the first conduction type, NaOH solution damages layer to described monocrystalline silicon piece and removes, and subsequently described monocrystalline silicon piece is carried out to washed with de-ionized water and drying and processing;
(2) silicon chip is sent into stopped pipe high temperature dispersing furnace front side of silicon wafer is carried out to diffusion technology;
(3) anti-etching technique, forms high-doped zone and doped regions;
(4) deposition anti-reflective film;
It is characterized in that, described diffusion technology is two step diffusions, and comprises: with nitrogen, for taking phosphorus gas, phosphorus oxychloride is phosphorus source, carries out constant temperature and tentatively spread within the scope of 950-1050 degree celsius temperature; With constant speed, cool to final temperature afterwards, advance diffusion simultaneously, when temperature arrives final temperature, stop logical phosphorus source.
2. preparation method of solar battery as claimed in claim 1, described preliminary diffusion and to advance summation diffusion time of diffusion be 25 minutes, stopping diffusion temperature is 750 degrees Celsius, and advance time of diffusion be preliminary diffusion time 1.5-2 doubly.
3. preparation method of solar battery as claimed in claim 2, between step (2) and step (3), also comprise that front electrode forms step, described front electrode forms step and comprises: the front-side etch in described monocrystalline silicon piece doped region forms front electrode channel patterns, and the degree of depth of described front electrode groove is described junction depth 1/4th to 1/2nd; And fill silver paste in the groove of this front electrode channel patterns.
4. preparation method of solar battery as claimed in claim 3 is filled silver paste and is carried out sintering processes afterwards to form front electrode in the groove of front electrode channel patterns.
5. preparation method of solar battery as claimed in claim 4, described front electrode channel patterns comprises: a plurality of side-wall electrode sheet grooves pair that are parallel to each other, each side-wall electrode sheet groove is to having two side-wall electrode sheet grooves that are parallel to each other, side-wall electrode sheet groove extends to opposite side by a side of front side of silicon wafer, a plurality of side-wall electrode sheet grooves between distance be greater than the distance between side-wall electrode sheet groove centering side-wall electrode sheet groove.
6. preparation method of solar battery as claimed in claim 5, described side-wall electrode sheet groove between distance be described side-wall electrode sheet groove to described in 2 times of distance between side-wall electrode sheet groove.
7. the preparation method of solar battery as described in claim 5-6, between the described side-wall electrode sheet groove of described a plurality of side-wall electrode sheet groove centerings, also there is the intercalation electrode sheet groove extending along broken line mode, this intercalation electrode sheet groove is communicated with described side-wall electrode sheet groove at knuckle place, and described many main electrode bar grooves are through this knuckle place; Corresponding, after described sintering processes, the silver paste in described side-wall electrode sheet groove, main electrode bar groove and intercalation electrode sheet groove forms respectively side-wall electrode sheet, main electrode bar and the intercalation electrode sheet in front electrode.
8. preparation method of solar battery as claimed in claim 7, described anti-etching technique comprises: at front side of silicon wafer, use anti-etching mask pattern coated electrode region, described electrode zone refers to: the region between two side-wall electrode sheets of the side-wall electrode sheet of a plurality of side-wall electrode sheet centerings and side-wall electrode centering, and main electrode bar region; Dry etching is carried out in front side of silicon wafer region to the doping not covered by anti-etching mask pattern, and etch depth is identical with the degree of depth of front electrode, etches into the position parallel with front electrode bottom always; Clean, remove anti-resistant layer, so far by described doped region, formed heavily doped region and doped regions, completed the preparation of selective emitting electrode structure;
Wherein said side-wall electrode sheet is to referring to the combination that has comprised two side-wall electrode sheets internally being formed by side-wall electrode sheet groove.
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| CN101794845A (en) * | 2010-03-15 | 2010-08-04 | 常州天合光能有限公司 | Method for preparing selective emitter by one-time diffusion |
| CN103346205A (en) * | 2013-06-08 | 2013-10-09 | 中山大学 | Method for preparing crystalline silicon solar cell with cross vertical emitting electrode structure |
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