CA1150367A - Circuit for odd frequency division of a given pulse train - Google Patents
Circuit for odd frequency division of a given pulse trainInfo
- Publication number
- CA1150367A CA1150367A CA000373034A CA373034A CA1150367A CA 1150367 A CA1150367 A CA 1150367A CA 000373034 A CA000373034 A CA 000373034A CA 373034 A CA373034 A CA 373034A CA 1150367 A CA1150367 A CA 1150367A
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- Canada
- Prior art keywords
- pulse train
- output
- input terminal
- shift register
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
- H03K23/505—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is an odd number
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- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
ABSTRACT
Disclosed is a circuit for odd frequency division of a given pulse train which provides an output pulse train having a duty ratio of fifty percent. For (2N-1) division (N is a plural number), N-delay type flip-flops are connected in cascade to form a shift register, each flip-flop having a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train at the signal input terminal, a non-inverting output terminal and an inverting output terminal.
The output from the inverting terminal of the last flip-flop is fed back to the signal input terminal of the first flip-flop. An Exclusive OR circuit has a first input terminal for receiving a pulse train to be frequency-divided and a second input terminal for receiving a pulse train from the inverting or non-inverting output terminal of a predetermined flip-flop of the shift register.
The Exclusive OR supplies a clock pulse train for frequency dividing to all the clock input terminals of the shift register so that first and second output pulse trains are produced from each of the flip-flops of the shift register.
Disclosed is a circuit for odd frequency division of a given pulse train which provides an output pulse train having a duty ratio of fifty percent. For (2N-1) division (N is a plural number), N-delay type flip-flops are connected in cascade to form a shift register, each flip-flop having a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train at the signal input terminal, a non-inverting output terminal and an inverting output terminal.
The output from the inverting terminal of the last flip-flop is fed back to the signal input terminal of the first flip-flop. An Exclusive OR circuit has a first input terminal for receiving a pulse train to be frequency-divided and a second input terminal for receiving a pulse train from the inverting or non-inverting output terminal of a predetermined flip-flop of the shift register.
The Exclusive OR supplies a clock pulse train for frequency dividing to all the clock input terminals of the shift register so that first and second output pulse trains are produced from each of the flip-flops of the shift register.
Description
` ~150367 :`
This invention relates to a circuit for odd frequency division of a given pulse train, and more particularl~, to a circuit for performing the odd frequency division of the pulse train ~referred to as "OF-divider" hereunder so that the resulting output pulse train has a duty ratio of fifty percent.
: Generally, in MODEM (modulator and demodulator) for data trans-mission and the like systems, various timing signals for s~stem control are pro-;~ duced by dividing given clock pulses in an odd or even dividing ratio.
One typical example of such a circuit for even frequency division of a given pulse train ~referred to as "EF-divider") is proposed in the United ` 10 5tates Patent No. 4,150,305 of Streit et al, issued April 17, 1979 ~Reference 1).
The proposed EF-divider can be effectively used to produce such timing signals, because it achieves the frequency division in a duty ratio of fifty percent (a 5~% duty ratio~ to facilitate the formation of the timing signal.
; Mean~hile, one example of such an OF-divider is described on pages 1-52 to 1-62 of "Digital Integrated Circuits," published in 1972 b~ National Semiconductor Corpoxation (Reference 2). However, since this divider does not achieve the frequenc~ division with a 50% dut~ ratio, it cannot be applied to the production of an accurate timing signal. Also, to provide a pulse train with such a duty ratio, a 1/2 frequency divider for providing a frequenc~-dividing ratio of 1 to 2 is additionally needed, resulting in a complicated device as a whole.
~ ne object of the present invention is, therefore, to provide a simplified OF-divider capable of producing a pulse train with a 50% dut~ ratio.
, According to one aspect of the invention, there is provided an O~-divider for perfoxming the odd frequency division of a given pulse train in a 5Q% dut~ ratio, which comprises a ~2N-l) frequency divider composed of a shift register of N-dela~
~, :
, ., .~ .
type flip-flops connected in cascade ~ is a plural number), each of which has a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train given to said signal input terminal, a non-inverting output terminal for producing a first output pulse train having the same phase as that of said pulse train given to the ~ignal input terminal, and an inverting output terminal for producing a second output pulse train having the reverse phase to that of the input pulse train, and means for feeding back the second output pulse train taken from the inverting terminal of the last flip-flop of the shift register to the signal input terminal of the initial flip-flop of the shift register; and an Exclusive OR circuit having a first input terminal for receiving the given input pulse train to be frequency-divided, a second input terminal for receiving a pulse train given from an output terminal of a predeter-mined flip-flop of the shift register, the Exclusive OR circuit supplying a clock pulse train for frequenc~ dividing to all the clock input terminals of the shift register so that said first and second output pulse trains are produced from each of the flip-flops of the shift register.
~ The invention will be described in greater detail in conjunction w~th the accompan~ing dra~ings, in ~hich:
.. 20 Figure 1 is a block diagram of one embodiment of the present ; invention;
Figure 2 shows waveforms for descri~ing the operation of the ~igùre 1 circuit;
Figure 3 is a block diagram of a second embodiment;
Pigure 4 shows ~aveforms for describing the operation of the i Pigure 3 circuit;
Figure 5 is a block diagram of a third embodiment; and
This invention relates to a circuit for odd frequency division of a given pulse train, and more particularl~, to a circuit for performing the odd frequency division of the pulse train ~referred to as "OF-divider" hereunder so that the resulting output pulse train has a duty ratio of fifty percent.
: Generally, in MODEM (modulator and demodulator) for data trans-mission and the like systems, various timing signals for s~stem control are pro-;~ duced by dividing given clock pulses in an odd or even dividing ratio.
One typical example of such a circuit for even frequency division of a given pulse train ~referred to as "EF-divider") is proposed in the United ` 10 5tates Patent No. 4,150,305 of Streit et al, issued April 17, 1979 ~Reference 1).
The proposed EF-divider can be effectively used to produce such timing signals, because it achieves the frequency division in a duty ratio of fifty percent (a 5~% duty ratio~ to facilitate the formation of the timing signal.
; Mean~hile, one example of such an OF-divider is described on pages 1-52 to 1-62 of "Digital Integrated Circuits," published in 1972 b~ National Semiconductor Corpoxation (Reference 2). However, since this divider does not achieve the frequenc~ division with a 50% dut~ ratio, it cannot be applied to the production of an accurate timing signal. Also, to provide a pulse train with such a duty ratio, a 1/2 frequency divider for providing a frequenc~-dividing ratio of 1 to 2 is additionally needed, resulting in a complicated device as a whole.
~ ne object of the present invention is, therefore, to provide a simplified OF-divider capable of producing a pulse train with a 50% dut~ ratio.
, According to one aspect of the invention, there is provided an O~-divider for perfoxming the odd frequency division of a given pulse train in a 5Q% dut~ ratio, which comprises a ~2N-l) frequency divider composed of a shift register of N-dela~
~, :
, ., .~ .
type flip-flops connected in cascade ~ is a plural number), each of which has a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train given to said signal input terminal, a non-inverting output terminal for producing a first output pulse train having the same phase as that of said pulse train given to the ~ignal input terminal, and an inverting output terminal for producing a second output pulse train having the reverse phase to that of the input pulse train, and means for feeding back the second output pulse train taken from the inverting terminal of the last flip-flop of the shift register to the signal input terminal of the initial flip-flop of the shift register; and an Exclusive OR circuit having a first input terminal for receiving the given input pulse train to be frequency-divided, a second input terminal for receiving a pulse train given from an output terminal of a predeter-mined flip-flop of the shift register, the Exclusive OR circuit supplying a clock pulse train for frequenc~ dividing to all the clock input terminals of the shift register so that said first and second output pulse trains are produced from each of the flip-flops of the shift register.
~ The invention will be described in greater detail in conjunction w~th the accompan~ing dra~ings, in ~hich:
.. 20 Figure 1 is a block diagram of one embodiment of the present ; invention;
Figure 2 shows waveforms for descri~ing the operation of the ~igùre 1 circuit;
Figure 3 is a block diagram of a second embodiment;
Pigure 4 shows ~aveforms for describing the operation of the i Pigure 3 circuit;
Figure 5 is a block diagram of a third embodiment; and
-2-.
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ll~V367 Figure 6 shows waveforms for describing the operation of the ; circuit shown in Figure 5.
Referring to Figure 1, one embodiment designed to function as a ` 1/3 frequency divider comprises an input terminal 15, an output terminal 16, a 1~4 frequency divider 13 composed of a shift register of tuo dela~-type flip-flops (FFs~ 11 and 12, and an Exclusive OR circuit ~EOR~ 14. The FF 11 has a signal input terminal lla, a clock input termlnal llb, a non-inverting output terminal llc, and an inverting output terminal lld, ~hereas the FF 12 has corre-sponding terminals 12a to 12d to those of the FF 11. The terminal 12d of the FF
12 ls connected to the terminal lla of the FF 11. The EOR 14 has two input terminals 14a and 14b, and an output terminal 14c. The input terminal 14a is connected to an input terminal 15 for receiving an input pul~e train to be divided, while the input terminal 14b is connected to the non-inverting output terminal 12c of ~F 12~ Also, the output terminal 14c is connected to the clock input terminals llb and 12b of the FF's 11 and 12. Each of the FF's 11 and 12 may be composed of the type shown on Pagesl-44 of Reference 2.
Referring no~ to Figure 2, the operation of the embodiment shown in Figure 1 ~ill be described hereunder. Waveforms ~A) to ~E) shown ~ correspond to ~ignals ~A), ~B~, ~C~, ~D~ and ~E) indicated in Figure 1, respective-.~ 20 1~. Each of symbols Tl to T6 indicates an equal period ~of time) ranging from "
th~ leading edge of a pulse to that of the next corresponding pulse in the input pulse train ~A~.
It ii~ assumed no~ that the outputs ~C) and ~D) given from the ~non-inverting output~ terminals llc and 12c assume ~logical) "Os" in the period TQ, whereas the output ~E~ of the ~inverting~ output terminals 12d, ~logical~ "1".
The EOR 14 functions as a signal path or an inverter for the pulse train ~A~ at the input terminal 15 in response to "0" or "1" from the output terminal 12c, , ~ ~ .
.-.......... j . , , ; ::
~5~367 respectively.
~ ith a pulse Pl of the pulse train (A) given to the t0rminal 15, the EOR 14 functions as the signal path with a delay of dl for the pulse Pl because of the "O" output (D) applied at 14b. The FF 11 stores the "1" output (E~ after a delay of d2, in response to the "1" output ~B), ~hereas the FF 12 stores the "O" output (C) after the delay of d2 because of the "1" output (B) at its clock input 12b.
At the trailing edge of the pulse Pl, the EOR 14 permits the "O"
shown ~y POl to pass therefrom after the delay of dl because the "O" output ~D) i5 still applied at 14b. A pulse P2 is then outputted from the EOR 14 after the delay of d2 by the output (D) kept at "O" at the leading edge of the pulse P2.
The output (D) then becomes "1" after the delay of d2 of the FF 12 in response to "1" of the output (B) and the output (C) which, at this time, is a "1". Next, the "1" output (D) is fed back to the EOR 14 to change the pulse P2 into "O" after a delay of (dl ~ d2).
~ ith "O" shown at PO2, the EOR 14 functions as an inverter to change the "O" of the pulse PO2 into "1", after a dela~ of dl, because of the output (D~ which is still "1". The output ~C) then becomes "O" after the delay of d2, in response to the "1" of the output ~B), ~hereas the output ~D) is kept at "1".
In re~ponse to a pulse P3, the EOR 14 produces "O" as the output ~B) after the delay of dl. At this time, the outputs (C) and ~D) remain at "O"
and "1", respectively.
As soon as "O" sho~n at PO3 is then given to the EOR 14, "1" is produced from the EOR 14 after the delay of dl by the output (D) kept at "1" at the trailing edge of the pulse P3. The output ~D) then becomes "O" after the delay of d2, in response to "1" of the output ~B), whereas the output ~C) is kept 115~)367 at "O". Next, "O" of the output (D) is given to the EOR 14 to allow the pulse P3 to pass therethrough as the output ~B). As a result, the FFs 11 and 12 are returned to the initial states ~ith the outputs ~C) and ~D) kept at ~~I and the output ~E) kept at "1". The above-mentioned ~frequency-dividing) operation is performed over the continuous periods Tl to T3. Similar operation is repeated over subsequent periods T4 to T6, etc.
Next, referring to Figure 3, the second embodiment has almost the same structure as that shown in Figure 1 except that one of the input terminals of the EOR 14 i5 connected to the inverting output terminal 12d of the FF 12.
The operation of this embodiment is almost the same as that of the embodiment of Figure 2 except that each of the outputs ~C), ~D), and ~E) becomes "1" after a dela~ of one half of the period Tl, because the output ~B) is kept at "O" until the pulse Pl becomes "1" ~see Flgure 4~. Therefore, detailed description of the operation of the Figure 5 embodiment ~ill be omitted here.
Like~ise, Figure 5 shows the third embodiment with a similar structure to that of Figure 1 except that one of the input terminals of the EOR
14 is connected to the output terminal of the FF 11.
It is assumed no~ that the initial states of the FFs 11 and 12 are the same as those in the case of Figure 1.
Referring to Figures 5 and 6, with the pulse Pl of the pulse train ~A~ given at the terminal 15, the EOR 14 functions as a signal path ~ith the dela~ of dl for the pulce Pl by "O" of the output ~C~. The output ~C) then becomes ~'1" after the dela~ of d2, in response to "1" of the output ~B~. At this time, the output ~D~ is kept at "O". The EOR 14 functions as an inverter to change "O"
of the pulse Pl into "1" after the delay of ~dl ~ d2) in response to "1" of the output (C).
At the trailing edge of the pulse Pl, the EOR 14 permits "O"
: -5-;
llS~367 shown by POl to be inverted after the delay of dl b~ the "1" output (C). The FF
11 stores "1" of the output (E~ after the dela~ of d2 in response to "1" of the output ~B). At this time, the output ~C~ is kept at "1". The pulse P2 is invert-ed by the EOR 14 after the delay of d2 by the output ~C) kept at "O" at the lead-. ing edge of the pulse P2.
Upon receipt of "O" sho~n by P02, the EOR 14 functions as theinverter to change "O" of the pulse P02 into "1" after the delay of dl by the output ~C) kept at "1". The output ~C) then becomes "0" after the delay of d2 of the FF12, in response to "1" of the output ~B), ~hereas the output ~D~ is kept at "1". Then, "O" of the output ~C) is ed to the EOR 14 to allo~ the pulse P02 to pass after the dela~ of ~dl ~ d2).
In response to a pulse P3, the EOR 14 produces "1" as the output ~B) after the dela~ of dl, while the output ~C~ remains at "O" and the output ~D) becomes "O" after the dela~ d2 in response to "1" of the output ~B).
As soon as "O" sho~n at PO3 is then given to the EOR 14, "O" is produced fr~m the EOR 14 after the delay of dl by the output ~C~ kept at "O".
i As a result, the FFs 11 and 12 arP returned to their initial states ~ith the outputs ~C) and ~D) at "O", and the output ~E) at "1". Such frequenc~-dividing operation is performed over the continuous periods Tl to T3.
Similar operation is done over subsequent periods T4 to 16, etc.
Although, in the above-discussed embodiment of Figure 5, the output (C~ of the FF 11 is given to the EOR 14, and inverting output ~not shown) of the PF 11 ma~ be given instead. In this modification, the same waveforms as the waveforms ~B) to (E) sho~n in Figure 6 are produced after a dela~ of one half of ~he period Tl.
Also~ each of the embodiments is directed to a 1/3 frequency divider, but arbitrary odd dividing ratios can be easil~ achieved by increasing the number of FFs used.
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ll~V367 Figure 6 shows waveforms for describing the operation of the ; circuit shown in Figure 5.
Referring to Figure 1, one embodiment designed to function as a ` 1/3 frequency divider comprises an input terminal 15, an output terminal 16, a 1~4 frequency divider 13 composed of a shift register of tuo dela~-type flip-flops (FFs~ 11 and 12, and an Exclusive OR circuit ~EOR~ 14. The FF 11 has a signal input terminal lla, a clock input termlnal llb, a non-inverting output terminal llc, and an inverting output terminal lld, ~hereas the FF 12 has corre-sponding terminals 12a to 12d to those of the FF 11. The terminal 12d of the FF
12 ls connected to the terminal lla of the FF 11. The EOR 14 has two input terminals 14a and 14b, and an output terminal 14c. The input terminal 14a is connected to an input terminal 15 for receiving an input pul~e train to be divided, while the input terminal 14b is connected to the non-inverting output terminal 12c of ~F 12~ Also, the output terminal 14c is connected to the clock input terminals llb and 12b of the FF's 11 and 12. Each of the FF's 11 and 12 may be composed of the type shown on Pagesl-44 of Reference 2.
Referring no~ to Figure 2, the operation of the embodiment shown in Figure 1 ~ill be described hereunder. Waveforms ~A) to ~E) shown ~ correspond to ~ignals ~A), ~B~, ~C~, ~D~ and ~E) indicated in Figure 1, respective-.~ 20 1~. Each of symbols Tl to T6 indicates an equal period ~of time) ranging from "
th~ leading edge of a pulse to that of the next corresponding pulse in the input pulse train ~A~.
It ii~ assumed no~ that the outputs ~C) and ~D) given from the ~non-inverting output~ terminals llc and 12c assume ~logical) "Os" in the period TQ, whereas the output ~E~ of the ~inverting~ output terminals 12d, ~logical~ "1".
The EOR 14 functions as a signal path or an inverter for the pulse train ~A~ at the input terminal 15 in response to "0" or "1" from the output terminal 12c, , ~ ~ .
.-.......... j . , , ; ::
~5~367 respectively.
~ ith a pulse Pl of the pulse train (A) given to the t0rminal 15, the EOR 14 functions as the signal path with a delay of dl for the pulse Pl because of the "O" output (D) applied at 14b. The FF 11 stores the "1" output (E~ after a delay of d2, in response to the "1" output ~B), ~hereas the FF 12 stores the "O" output (C) after the delay of d2 because of the "1" output (B) at its clock input 12b.
At the trailing edge of the pulse Pl, the EOR 14 permits the "O"
shown ~y POl to pass therefrom after the delay of dl because the "O" output ~D) i5 still applied at 14b. A pulse P2 is then outputted from the EOR 14 after the delay of d2 by the output (D) kept at "O" at the leading edge of the pulse P2.
The output (D) then becomes "1" after the delay of d2 of the FF 12 in response to "1" of the output (B) and the output (C) which, at this time, is a "1". Next, the "1" output (D) is fed back to the EOR 14 to change the pulse P2 into "O" after a delay of (dl ~ d2).
~ ith "O" shown at PO2, the EOR 14 functions as an inverter to change the "O" of the pulse PO2 into "1", after a dela~ of dl, because of the output (D~ which is still "1". The output ~C) then becomes "O" after the delay of d2, in response to the "1" of the output ~B), ~hereas the output ~D) is kept at "1".
In re~ponse to a pulse P3, the EOR 14 produces "O" as the output ~B) after the delay of dl. At this time, the outputs (C) and ~D) remain at "O"
and "1", respectively.
As soon as "O" sho~n at PO3 is then given to the EOR 14, "1" is produced from the EOR 14 after the delay of dl by the output (D) kept at "1" at the trailing edge of the pulse P3. The output ~D) then becomes "O" after the delay of d2, in response to "1" of the output ~B), whereas the output ~C) is kept 115~)367 at "O". Next, "O" of the output (D) is given to the EOR 14 to allow the pulse P3 to pass therethrough as the output ~B). As a result, the FFs 11 and 12 are returned to the initial states ~ith the outputs ~C) and ~D) kept at ~~I and the output ~E) kept at "1". The above-mentioned ~frequency-dividing) operation is performed over the continuous periods Tl to T3. Similar operation is repeated over subsequent periods T4 to T6, etc.
Next, referring to Figure 3, the second embodiment has almost the same structure as that shown in Figure 1 except that one of the input terminals of the EOR 14 i5 connected to the inverting output terminal 12d of the FF 12.
The operation of this embodiment is almost the same as that of the embodiment of Figure 2 except that each of the outputs ~C), ~D), and ~E) becomes "1" after a dela~ of one half of the period Tl, because the output ~B) is kept at "O" until the pulse Pl becomes "1" ~see Flgure 4~. Therefore, detailed description of the operation of the Figure 5 embodiment ~ill be omitted here.
Like~ise, Figure 5 shows the third embodiment with a similar structure to that of Figure 1 except that one of the input terminals of the EOR
14 is connected to the output terminal of the FF 11.
It is assumed no~ that the initial states of the FFs 11 and 12 are the same as those in the case of Figure 1.
Referring to Figures 5 and 6, with the pulse Pl of the pulse train ~A~ given at the terminal 15, the EOR 14 functions as a signal path ~ith the dela~ of dl for the pulce Pl by "O" of the output ~C~. The output ~C) then becomes ~'1" after the dela~ of d2, in response to "1" of the output ~B~. At this time, the output ~D~ is kept at "O". The EOR 14 functions as an inverter to change "O"
of the pulse Pl into "1" after the delay of ~dl ~ d2) in response to "1" of the output (C).
At the trailing edge of the pulse Pl, the EOR 14 permits "O"
: -5-;
llS~367 shown by POl to be inverted after the delay of dl b~ the "1" output (C). The FF
11 stores "1" of the output (E~ after the dela~ of d2 in response to "1" of the output ~B). At this time, the output ~C~ is kept at "1". The pulse P2 is invert-ed by the EOR 14 after the delay of d2 by the output ~C) kept at "O" at the lead-. ing edge of the pulse P2.
Upon receipt of "O" sho~n by P02, the EOR 14 functions as theinverter to change "O" of the pulse P02 into "1" after the delay of dl by the output ~C) kept at "1". The output ~C) then becomes "0" after the delay of d2 of the FF12, in response to "1" of the output ~B), ~hereas the output ~D~ is kept at "1". Then, "O" of the output ~C) is ed to the EOR 14 to allo~ the pulse P02 to pass after the dela~ of ~dl ~ d2).
In response to a pulse P3, the EOR 14 produces "1" as the output ~B) after the dela~ of dl, while the output ~C~ remains at "O" and the output ~D) becomes "O" after the dela~ d2 in response to "1" of the output ~B).
As soon as "O" sho~n at PO3 is then given to the EOR 14, "O" is produced fr~m the EOR 14 after the delay of dl by the output ~C~ kept at "O".
i As a result, the FFs 11 and 12 arP returned to their initial states ~ith the outputs ~C) and ~D) at "O", and the output ~E) at "1". Such frequenc~-dividing operation is performed over the continuous periods Tl to T3.
Similar operation is done over subsequent periods T4 to 16, etc.
Although, in the above-discussed embodiment of Figure 5, the output (C~ of the FF 11 is given to the EOR 14, and inverting output ~not shown) of the PF 11 ma~ be given instead. In this modification, the same waveforms as the waveforms ~B) to (E) sho~n in Figure 6 are produced after a dela~ of one half of ~he period Tl.
Also~ each of the embodiments is directed to a 1/3 frequency divider, but arbitrary odd dividing ratios can be easil~ achieved by increasing the number of FFs used.
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Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A circuit for odd frequency division of a given input pulse train in a duty ratio of 50 percent, comprising:
a (2N-1) frequency divider composed of a shift register of N-delay type flip-flops connected in cascade (N is a plural number), each of which has a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train given to said signal input terminal, a non-inverting output terminal for producing a first output pulse train having the same phase as that of said pulse train given to the signal input terminal, and an inverting output terminal for producing a second output pulse train having the reverse phase to that of the in-put pulse train, and means for feeding back the second output pulse train taken from the inverting terminal of the last flip-flop of the shift register to the signal input terminal of the initial flip-flop of the shift register; and an Exclusive OR circuit having a first input terminal for receiving the given input pulse train to be frequency-divided, a second input terminal for receiving a pulse train given from an output terminal of a predeter-mined flip-flop of the shift register, the Exclusive OR circuit supplying a clock pulse train for frequency dividing to all the clock input terminals of the shift register so that said first and second output pulse trains are produced from each of the flip-flops of the shift register.
a (2N-1) frequency divider composed of a shift register of N-delay type flip-flops connected in cascade (N is a plural number), each of which has a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train given to said signal input terminal, a non-inverting output terminal for producing a first output pulse train having the same phase as that of said pulse train given to the signal input terminal, and an inverting output terminal for producing a second output pulse train having the reverse phase to that of the in-put pulse train, and means for feeding back the second output pulse train taken from the inverting terminal of the last flip-flop of the shift register to the signal input terminal of the initial flip-flop of the shift register; and an Exclusive OR circuit having a first input terminal for receiving the given input pulse train to be frequency-divided, a second input terminal for receiving a pulse train given from an output terminal of a predeter-mined flip-flop of the shift register, the Exclusive OR circuit supplying a clock pulse train for frequency dividing to all the clock input terminals of the shift register so that said first and second output pulse trains are produced from each of the flip-flops of the shift register.
2. A circuit as claimed in claim 1 wherein N = 2.
3. A circuit as claimed in claim 1 or 2 wherein the second input terminal of the Exclusive OR circuit receives a pulse train from an inverting output terminal of a predetermined flip-flop of the shift register.
4. A circuit as claimed in claim 1 or 2 wherein the second input terminal of the Exclusive OR circuit receives a pulse train from a non-invertingoutput terminal of a predetermined flip-flop of the shift register.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3267580A JPS56129431A (en) | 1980-03-17 | 1980-03-17 | Frequency dividing circuit for odd number |
| JP32675/1980 | 1980-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1150367A true CA1150367A (en) | 1983-07-19 |
Family
ID=12365442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000373034A Expired CA1150367A (en) | 1980-03-17 | 1981-03-16 | Circuit for odd frequency division of a given pulse train |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS56129431A (en) |
| CA (1) | CA1150367A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242617A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Odd frequency dividing counter |
| JPS6381424U (en) * | 1986-11-12 | 1988-05-28 | ||
| JPS63185323U (en) * | 1987-05-20 | 1988-11-29 | ||
| JPH034618A (en) * | 1989-05-31 | 1991-01-10 | Nec Eng Ltd | Clock frequency division circuit |
| JPH04195999A (en) * | 1990-11-28 | 1992-07-15 | Fujitsu Ltd | Sequential logic circuit |
| US6995589B2 (en) * | 2003-06-13 | 2006-02-07 | Via Technologies Inc. | Frequency divider for RF transceiver |
-
1980
- 1980-03-17 JP JP3267580A patent/JPS56129431A/en active Pending
-
1981
- 1981-03-16 CA CA000373034A patent/CA1150367A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56129431A (en) | 1981-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |