JPS6381424U - - Google Patents
Info
- Publication number
- JPS6381424U JPS6381424U JP17354986U JP17354986U JPS6381424U JP S6381424 U JPS6381424 U JP S6381424U JP 17354986 U JP17354986 U JP 17354986U JP 17354986 U JP17354986 U JP 17354986U JP S6381424 U JPS6381424 U JP S6381424U
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- signal
- basic clock
- input
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案に係るプログラマブル・カウン
タの構成例を示す図、第２図と第３図は第１図装
置のタイムチヤート、第４図は先願のプログラマ
ブル・カウンタの構成を示す図、第５図は第４図
装置のタイムチヤート、第６図はプログラマブル
・カウンタの原理を説明するための図である。
１０……Ｎ検出手段、１１……設定手段、１２
〜１５……Ｄ―ＦＦ、２１〜２３……ゲート、２
４……フリツプフロツプ。
FIG. 1 is a diagram showing an example of the configuration of a programmable counter according to the present invention, FIGS. 2 and 3 are time charts of the device shown in FIG. 1, and FIG. 4 is a diagram showing the configuration of the programmable counter of the earlier application. FIG. 5 is a time chart of the device shown in FIG. 4, and FIG. 6 is a diagram for explaining the principle of the programmable counter. 10...N detection means, 11...setting means, 12
~15...D-FF, 21-23...Gate, 2
4...Flip-flop.
Claims (1)
分周器１２の出力が入力される同期式カウンタ１
３〜１５とを具備し、設定値信号により設定され
た分周比で入力信号ｓｋを分周するプログラマブ
ル・カウンタにおいて、 基本クロツク信号ｓＯと設定値信号を構成する
１ビツトの信号を導入し、基本クロツク信号ｓＯ
の位相を反転させて次段の前記分周器１２へ加え
るロジツク回路を備えたことを特徴とするプログ
ラマブル・カウンタ。[Claims for Utility Model Registration] A frequency divider 12 to which an input signal sk is applied, and a synchronous counter 1 to which the output of this frequency divider 12 is input.
Introducing a 1-bit signal constituting the basic clock signal sO and the set value signal, Basic clock signal sO
A programmable counter comprising a logic circuit for inverting the phase of the frequency divider 12 and applying it to the frequency divider 12 at the next stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17354986U JPS6381424U (en) | 1986-11-12 | 1986-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17354986U JPS6381424U (en) | 1986-11-12 | 1986-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6381424U true JPS6381424U (en) | 1988-05-28 |
Family
ID=31111112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17354986U Pending JPS6381424U (en) | 1986-11-12 | 1986-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6381424U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125755A (en) * | 1977-04-09 | 1978-11-02 | Tamura Electric Works Ltd | Frequency division counter |
| JPS56129431A (en) * | 1980-03-17 | 1981-10-09 | Nec Corp | Frequency dividing circuit for odd number |
-
1986
- 1986-11-12 JP JP17354986U patent/JPS6381424U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125755A (en) * | 1977-04-09 | 1978-11-02 | Tamura Electric Works Ltd | Frequency division counter |
| JPS56129431A (en) * | 1980-03-17 | 1981-10-09 | Nec Corp | Frequency dividing circuit for odd number |
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