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AU6940900A - Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same - Google Patents

Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same

Info

Publication number
AU6940900A
AU6940900A AU69409/00A AU6940900A AU6940900A AU 6940900 A AU6940900 A AU 6940900A AU 69409/00 A AU69409/00 A AU 69409/00A AU 6940900 A AU6940900 A AU 6940900A AU 6940900 A AU6940900 A AU 6940900A
Authority
AU
Australia
Prior art keywords
shrinkable
easy
memory cell
semiconductor memory
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU69409/00A
Other languages
English (en)
Inventor
Tao Cheng Lu
Hsiang Lan Lung
Mam Tsung Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix America Inc
Original Assignee
Macronix America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix America Inc filed Critical Macronix America Inc
Publication of AU6940900A publication Critical patent/AU6940900A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
AU69409/00A 1999-08-27 2000-08-25 Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same Abandoned AU6940900A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US38448099A 1999-08-27 1999-08-27
US09384480 1999-08-27
PCT/US2000/023504 WO2001017031A1 (en) 1999-08-27 2000-08-25 Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same

Publications (1)

Publication Number Publication Date
AU6940900A true AU6940900A (en) 2001-03-26

Family

ID=23517472

Family Applications (1)

Application Number Title Priority Date Filing Date
AU69409/00A Abandoned AU6940900A (en) 1999-08-27 2000-08-25 Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same

Country Status (4)

Country Link
JP (1) JP4969748B2 (ja)
CN (1) CN1229873C (ja)
AU (1) AU6940900A (ja)
WO (1) WO2001017031A1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4923321B2 (ja) * 2000-09-12 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置の動作方法
JP4608815B2 (ja) * 2001-06-08 2011-01-12 ソニー株式会社 不揮発性半導体記憶装置の製造方法
JP4393106B2 (ja) * 2003-05-14 2010-01-06 シャープ株式会社 表示用駆動装置及び表示装置、並びに携帯電子機器
US7312495B2 (en) 2005-04-07 2007-12-25 Spansion Llc Split gate multi-bit memory cell
CN100411144C (zh) * 2005-08-16 2008-08-13 力晶半导体股份有限公司 非挥发性存储器及其制造方法
JP2008053270A (ja) * 2006-08-22 2008-03-06 Nec Electronics Corp 半導体記憶装置、及びその製造方法
KR100843550B1 (ko) * 2006-11-06 2008-07-04 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조방법
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145080A (ja) * 1991-11-25 1993-06-11 Kawasaki Steel Corp 不揮発性記憶装置
JPH05251669A (ja) * 1992-03-06 1993-09-28 Matsushita Electron Corp 半導体記憶装置およびその書き換え方法
EP0571692B1 (en) * 1992-05-27 1998-07-22 STMicroelectronics S.r.l. EPROM cell with a readily scalable down interpoly dielectric
JPH07169864A (ja) * 1993-12-16 1995-07-04 Kawasaki Steel Corp 不揮発性半導体記憶装置
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device
US5783849A (en) * 1996-02-23 1998-07-21 Citizen Watch Co., Ltd. Semiconductor device
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5969383A (en) * 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
US5879993A (en) * 1997-09-29 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride spacer technology for flash EPROM
US6020606A (en) * 1998-03-20 2000-02-01 United Silicon Incorporated Structure of a memory cell
JP3973819B2 (ja) * 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Also Published As

Publication number Publication date
CN1375114A (zh) 2002-10-16
JP2003508921A (ja) 2003-03-04
JP4969748B2 (ja) 2012-07-04
CN1229873C (zh) 2005-11-30
WO2001017031A1 (en) 2001-03-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase