NL7902878A - Semiconductor prodn. method using etched layers - obtaining silicon-oxide layer by thermal oxidation following ion implantation in non-oxidised layers - Google Patents

Abstract

In the semiconductor device, an insulating layer is applied to the surface of part of the silicon substrate. The insulating layer is covered with a silicon layer etched into a pattern is then provided with a silicon oxide layer obtained by thermal oxidation. The silicon zone underneath the insulating layer remains unoxidised during the oxidation process. Ion implantation will take place through the insulating layer (4) after the pattern has been etched into the silicon layer (1) and before thermal oxidation takes place. The oxidation inhibiting ions will be on the surface of the silicon layer on both sides of the silicon pattern.

Description

e. 4 N.V. Philips · Incandescent lamp factories in Eindhoven.

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A method of manufacturing a semiconductor device.

The invention relates to a method for manufacturing a semiconductor device, in which an insulating layer is applied to the surface of at least a part of a semiconductor region of silicon, to which insulating layer is applied by means of a masking layer is etched in a pattern, after which the exposed surface of the silicon pattern is provided with a silicon oxide layer by thermal oxidation, during which oxidation the silicon region located below the insulating layer is practically not oxidized.

The invention further relates to a semiconductor device manufactured by applying the method.

A method of the described type is known from Dutch patent application 7116013. In this known method, an insulating layer of oxidation-preventing material, for example an silicon nitride layer, optionally located on and / or under a thin oxide layer, is applied to the silicon area. This insulating layer prevents the oxidation of the silicon surface located on either side of the pattern during the thermal oxidation of the silicon pattern applied to it. As a result, the silicon pattern can be provided with a relatively thick oxide layer without objection, which may be important, for example, 7 0 fl 9 7 (? I * 13. ^. 79 2 PHN 9414, if the silicon pattern is to be guided by an oxide conductor above this conductor layer. insulated, or when the oxidized silicon cartridge is to be used as an etching mask for etching contact windows into the insulating layer.

In practice, however, the aforementioned use of a silicon nitride layer often meets with drawbacks. For example, especially with MOS transistors, charge injection from the silicon substrate into the nitride layer at the side of the drain zone, where the field strength is high, can change the threshold voltage. Also, when the silicon pattern is used as the control electrode of a field-effect device, it is often difficult to combine the silicon nitride layer with the underlying oxide layer and any further layers, which together form the said insulating layer, the small thickness desired for the control electrode insulation. to give. Furthermore, with composite oxide-nitride layers, it is difficult to keep the number of surface states and interface states as low as when using a silicon oxide layer alone. In addition, in the case where contact windows are to be etched in the insulating layer above the non-oxidized silicon region, multiple etching steps are required to remove composite oxide-nitride layers.

It is further noted that German patent 2250129 discloses a method for forming oxide layers of different thickness on a silicon surface, by implanting locally oxidation-promoting oxidation-promoting ions and local oxidation-inhibiting ions into the surface. However, an application of this method for obtaining a relatively thick oxide layer on a silicon pattern which is separated by a thin oxide layer from an underlying silicon region, without noticeably oxidizing this silicon region, cannot be derived from this patent.

One of the objects of the invention is to provide a method for manufacturing a semiconductor device comprising an oxidized silicon pattern separated by an insulating layer from the underlying semiconductor surface of the 7902878 * * 13. ^. 79 3 PHN 9ΗλΚ without the need for the precipitation of a silicon nitride-containing layer.

According to the invention, a method of the S type described in the preamble is characterized in that an insulating layer of silicon oxide is applied and that after patterning the silicon layer and before the thermal oxidation in the presence of at least part of the masking layer via the insulating layer is applied by ion implantation in the surface of the silicon region on either side of the silicon pattern to inhibit oxidation-inhibiting ions, the parts of the masking layer present on the silicon pattern masking against this implantation.

It should be noted that ion implantation in this application also includes a thermal after-treatment associated with this implantation (so-called "annealing"). The oxidation-inhibiting ions can, for example, only penetrate into the silicon region during this thermal post-treatment by diffusion under conditions.

By using ion bombardment in the manner described, the use of silicon nitride-containing layers with the previously described associated drawbacks can be avoided, while still retaining all advantages with respect to self-alignment.

The invention can in principle be applied using any desired oxidation-inhibiting ion.

Preferably, however, nitrogen ions are used which do not act as donors or as acceptors and which have very good oxidation-inhibiting properties. Advantageously, an implantation energy is further chosen such that the maximum concentration of the oxidation inhibiting ions is within a distance of about 20 nm from the interface between the insulating oxide layer and the silicon region, either in the silicon region or in the oxide layer. . The concentration of the implanted oxidation-inhibiting ions at the interface between the insulating oxide layer and the silicon region is preferably at least 10 ions per 790 2 8 78 <% 13. ^. 79 ^ PHN 9k14 3 cm, in order to have an effective oxidation-inhibiting effect to obtain.

The inhibition of the thermal oxidation of silicon by implantation of, for example, nitrogen ions is much more effective when the nitrogen ions are implanted in or through a SiO 2 layer, such that the range of the implantation is close to the Si / SiO 2 interface. than when the same implantation with the same ion dose is applied to uncovered silicon, or to; Silicon covered with a layer of SiOg which is thin relative to the range of implantation.

A further preferred embodiment of the method according to the invention is characterized in that the silicon region is provided with an oxide pattern at least partly sunk in the region, which surrounds part of the silicon region, on which part the insulating layer of silicon lithium oxide is applied, and that the silicon pattern is partially applied to the sunken oxide pattern. This preferred embodiment not only gives a high packing density, but also allows a greater degree of self-alignment, especially in the case where contact windows are etched in the insulating layer. The sunken oxide pattern and / or the oxidized silicon pattern can then advantageously be used as an etching mask.

The invention will be further described with reference to some exemplary embodiments and the drawing, in which Figures 1 to 6A to 8B, 10A and 10B schematically show in cross section a field effect transistor with insulated control electrode ions in successive stages of manufacture according to the invention, Figures 5 and 9 show plan views of the field effect transistor in the stages of Figures 6A and 6B and Figures 10A and 1OB, respectively,

Figure 1OC shows a cross-section corresponding to Figure 1OA 35 in a variant of the method according to the invention, Figures 11 to 16 schematically show in cross-section a charge-coupled device (CCD) in successive stages of manufacture according to the invention, 790 28 78 * * 13 - ^. 79 5 PHN 9 ^ k

Figure 17 shows oxidation characteristics of silicon with and without nitrogen ion implantation,

Figure 18 shows oxidation characteristics of silicon bombarded with nitrogen ions through different oxide thicknesses, and

Figure 19 schematically shows a cross-section through another semiconductor device at a stage of manufacture according to a variant of the invention.

The figures are schematic and not drawn to scale 10, in particular the dimensions in the thickness direction are greatly exaggerated.

Figures 1 to 10B schematically show successive stages of a first embodiment of the method according to the invention, in which an MOS transistor is manufactured.

It is assumed (see Fig. 1) a semiconductor body with a semiconductor region 1 of silicon. In this example, the entire semiconductor body is made of silicon, although this is by no means necessary. The silicon region 1 shown in the drawing consists, for example, of 20 p-type silicon with a resistivity of 30 ohm cm. The region 1 can be, for example, an epitaxial layer, but it can also be formed by a homogeneous single crystalline silicon wafer, as in the case discussed here. The region 1 is selectively oxidized to provide an oxide cartridge 2, which has a thickness of about 2 microns and is sunk into the region 1 over a depth of about 1 micron.

In this example, the oxide pattern 2 surrounds a square part of the silicon region 1. The periphery of this part is indicated by a in top view in Figures 5 and 9.

The application of the oxide pattern 2 is effected in a manner generally customary in the semiconductor technique, as described in Philips Research Reports, Vol. 25, 1970, pp. II8-132. The manner of applying this countersunk oxide pattern is of no further importance for the invention and will therefore not be described in detail here. Instead of a countersunk oxide cartridge, an oxide cartridge can also be provided which does not extend below the silicon surface 3, for example by pyrolithic deposition of 7902878 13. 79 6 PHN 9kI, t, fc oxide, or by first the entire surface of a 2 µm provide a thick oxide layer and etch it away within said square area.

An insulating layer k is now applied to the surface 3 of the silicon region 1 (see Fig. 2), by thermal oxidation at 950 ° in dry oxygen for 135 minutes. The oxide layer k has a thickness of 0.07 µm.

Then (see Fig. 3) = on * the insulating layer k (and also on the oxide pattern - 2) - a layer "5 of", ptolykris-: · "10 talline silicon is deposited, according to the semiconductor In general, conventional methods The silicon layer 5 in this example is N-type conductive, has a thickness of, for example, 0.5 ^ υ · ΐη and has a layer resistance of about 30 ohms per square.

The silicon layer 5 is then provided with a 0.2 µm thick layer 6 of silicon oxide by thermal oxidation, see Fig. k,

The oxide layer 6 is now reduced in thickness to about 0.05 µm at the location where a contact window will later have to be provided on the control electrode of the MOS transistor. For this purpose (see Fig. 6a and 6b) the oxide layer 6 is covered with a photoresist layer 75 in which a window 8 (see Fig. 5 and Fig. 6b) is formed by exposure and development. Figure 6A schematically shows a cross-section along line AA ", and Figure 6B schematically shows a cross-section along line BB" of Figure 5. The oxide layer 6 is then etched away within the window 8 to a thickness of 0.05 µm, after which the photoresist mask 7 is removed. It is also possible to etch away the oxide layer 6 completely within the window 8 and to apply an oxide layer of 0.05 µm thickness again later by a light oxidation.

The silicon layer 6 with the oxide layer thereon is then etched into a pattern. This is done in the usual manner by locally etching away the oxide layer 6 and then the silicon layer 5 using a photoresist mask 35 (not shown). The photoresist mask can herein be removed after etching the oxide layer 6, after which the remaining parts of the layer 6 serve as masking 7902878 13.4.79 7 PHN 94i4 for pattern etching the silicon layer 5. The photoresist layer can also be left until after the etching of the silicon layer 5. Although this is not necessary, the oxide layer 4 on either side of the silicon pattern is then preferably etched thinly, for example up to 0.035 µm, so that the desired one can be implanted. ion dose at the silicon surface can be easily obtained.

After the pattern etching of the silicon layer 5 and the removal of the photoresist layer, in the presence of the parts of the oxide layer 6 lying on the silicon pattern, the entire surface is bombarded with oxidation-inhibiting ions, in this example nitrogen ions (12) according to arrows 12, with a dose of 4x101 ^ molecular nitrogen. j ,. 2 (Ng) ions per cm and an implantation energy of 50 keV.

This dose and energy are chosen such that the maximum concentration of the nitrogen atoms is within 20 nm of the interface between the layer 4 and the region 1, and such that the via the insulating layer 4 in the surface of the silicon region 1 applied nitrogen concentration after annealing (annealing) to reduce the crystal damage at the interface 3 between the oxide layer 4 and the underlying silicon region 1 is at least about 10 atoms per cm. This calcination usually takes place at 900 ° to 1000 ° in nitrogen for about 15 minutes, before the subsequent thermal oxidation. Within the part of the silicon region 1 surrounded by the oxide pattern 2, the thickness of the oxide layer 6 present on the silicon pattern 5 is so great that the layer 6 masks against the implantation. Therefore, in the cross section AA '(Figure 7A), the nitrogen ions 12 (indicated by the dotted line) practically all remain in the oxide 6. However, in the cross section BB1, where the oxide layer 6 is much thinner, the nitrogen ions penetrate into the surface of the silicon cartridge 5 (Fig. 7B).

Then, an oxidation is performed at 1000 ° C in moist oxygen for about 90 minutes. An oxide layer 13 of approximately 0.5 µm in thickness is formed on the exposed parts in the silicon pattern 5.

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The silicon region 1 located below the insulating layer 4 (Fig. 8a) and the part of the silicon cartridge 5 (Fig. 8B) lying under the diluted part of the oxide layer 6 are thereby virtually not oxidized, due to the nitrogen ion concentration applied.

The n-type supply and discharge zones 14 and 15 (Fig. 8a) can now be applied by implantation of, for example, arsenic ion in which · 1ΐ & ± · geo-cydened silicon cartridge 5, which among other things "forms" the control electrode ", and the - oxide-10 mask cartridge 2 against this implantation, at least in section AA * (Fig. 8a) If the thin portion of the oxide layer 6 in section BB '(Fig. 8b) does not mask against this implantation, a prior (non-critical) mask, for example a photoresist mask, must be applied.

When the silicon pattern 5 is already n-type conductive, as in this example, at the cross-section of FIG. 8B no masking required.

The order of the arsenic and nitrogen implants can also be reversed, so that after the construction of FIG. 7A and FIG. 7B, the supply and discharge zones are first formed, and then the nitrogen implantation takes place.

By a short etching process, which does not require an etching mask, the exposed parts of the oxide layer 4 as well as the thin part of the oxide layer 6 in section BB * (Fig. 8b) are now removed. This creates contact holes 16, 17 and 18 for the supply and discharge zones and on the control electrode. By depositing, for example, aluminum and etching, the charge, discharge and control electrode connections 19, 20 and 21 are then realized, in FIG. 9 indicated in hatched plan view. Fig. 10A and 10B show cross sections along the lines AA 'and BB' respectively in Figure 9 · This completes the MOS transistor.

According to a variant of the method (see 35 Fig. 10C), before applying the metallization, a thick silicon oxide layer 22 can be applied on the whole, for example by pyrolithic precipitation, after which contact windows are etched in this layer 22 using 790 2 8 78 13 * 4.79 9 PHN 94l4 a mask that is not critical and may be offset from the supply and discharge zones, as shown in Figure 10C.

In the example described, a combination of an oxide layer 6 and a photoresist mask was used for patterning the silicon layer. However, this is not necessary, and in the following example, in which a charge-coupled device is manufactured, the silicon pattern is obtained by using only a photoresist mask 10.

In this case too (see Figure 11), a p-type silicon region 31 »is assumed with a resistivity of, for example, 30 ohm.cm. As in the previous example, this region is provided with a partially embedded oxide pattern 32 in the silicon, which surrounds a rectangular, strip-shaped part of the region 1 of the surface. An insulating layer 34 of silicon oxide is applied to the surface 33, for example by thermal oxidation, with a thickness of, for example, also 0.07 µm.

A conductive layer 35 of n-type polycrystalline silicon is deposited on the layer jh, with a thickness of 0.5 µm and a layer resistance of, for example, 20 to 40 Ohm per square.

The silicon layer 35 is now patterned (see Figure 12) by means of a masking layer consisting of a photoresist mask 36 conventionally applied; this pattern contains a number of parallel and interconnected strips.

Subsequently, the surface (see Fig. 13) is subjected to a bombardment with arsenic ions 37 »with, for example, an energy of 150 keV and a dose of 4x10 2 ions per cm. The arsenic ions penetrate through the oxide layer 34 but are masked by the photoresist layer 36 and the oxide pattern 32. Approximately 0.35 µm deep n-35 type zones 38 are formed in the region 1.

Thereafter, in the presence of the masking layer 36, oxidation-inhibiting ions are introduced via the oxide layer 34 into the part of the surface of the region not covered by the silicon pattern 35 1 790 28 78 ψ> 13.4.79 10 ΡΗΝ 9414 (see Figpur 14) applied according to arrows 39 · These may again be nitrogen ions, with such energy that they penetrate through the layer 34 but not through the photoresist layer 36. It is also possible to select an energy and a dose in which the nitrogen ions do not yet penetrate completely through the layer 34, but are present in the concentration 34 at such a depth and depth that they the implantation annealing treatment (after removal of the photoresist mask 36) diffuses into the surface of the region 1. When the layer 34 is about 0.07 µm thick, the same dose and energy as in the previous example can be used. The annealing temperature and time can also have the same value. Upon annealing, the crystal damage formed upon implantation of the arsenic ions is also largely repaired. The location of the implanted surface nitrogen atoms is shown in FIG. 14 indicated by the dotted line 39 '.

After this, the exposed surface of the silicon cartridge 35 is provided with a 0.5 µm thick oxide layer 4θ by thermal oxidation in moist oxygen at 1000 ° C. for 90 minutes, see Figure 15 «Due to the presence of the oxidation-inhibiting nitrogen atoms« 39, the Parts of the surface covered by the silicon pattern 35 in this oxidation process are substantially not oxidized, so that the oxide layer 34 hardly increases in thickness.

After this thermal oxidation, a second conductive layer is applied, for example also a polycrystalline silicon layer, or an aluminum layer, from which a second conductor pattern 41 (see Figure 16) is formed by photolithographic etching. This second conductor pattern also contains a number of parallel strips. Prior to this, the silicon surface was first exposed, at the location of the extreme zones 38, by etching away the oxide layer 34, using a non-critical photoresist mask. As a result, the conductor pattern 41 connects to the extreme zones 38, and there forms the input I and the output 7902878 13.4.79 11 PHN 9414 U of the charge-coupled device, see Figure 16. The device thus obtained is a so-called two-phase charge-coupled device (CCD ); both electrodes 41 and electrodes 35 are connected to the clock voltage and 5 to the clock voltage every other, as schematically in

Figure 16 indicated. The operation of this charge-coupled device, with which information-carrying charge packets can be transported from the input terminal I to the output terminal ü has been described in detail in many places in the literature, see for example the book "Charge Transfer Devices" by C.H. Séquin and M.F. Torapsett, Jiew York 1975, in particular Chapter III A2, pp. 25-30, and therefore will not be discussed here further as it has no further connection with the invention. It is further noted that, if the arsenic implantation is omitted, the charge coupled device can also function, but with more than two clock voltages.

In this example, the invention has the important advantage that no silicon nitride-containing layer has to be deposited, while the insulation between the overlapping control electrodes 41 and 35 is nevertheless ensured by a sufficient thickness of the oxide layer 40, and the layer 34 below the control electrodes are thin enough (substantially as thick as under the control electrodes35) to allow efficient control with clock voltages that are not too high.

Although in this example only a small number of control electrodes are drawn for the sake of clarity of the drawing, this number will in reality usually be much larger.

The invention is not limited to the given exemplary embodiments, but can be applied in all cases where an oxidized silicon pattern is to be obtained without appreciable oxidation of the silicon surface located on either side of this pattern. In addition, the geometry of the device to be manufactured, the thicknesses of the silicon and silicon oxide layers and the doping concentrations used can be selected by the skilled person as required.

7902878 13.4.79 12 PHN 9414

As regards thermal oxidation, it has been noted that the inhibitory effect of implanted nitrogen ions has been found to be much stronger for an oxidation in dry oxygen than for an oxidation in moist oxygen. However, the oxidation times in dry oxygen are much longer. In Figure 17, the thickness d of the oxide layer is in µm on unimplanted n-type polycrystalline silicon with a layer resistance of 30 ohms per square (curve A) 16 2 and on with one. nitrogen ion dose -of -ifc. X. 4-0 - ions per 10 and 10 at 50 keV implanted single crystalline silicon covered with an oxide layer of 0.07 µm at the start of the oxidation (curve B) shown as a function of the oxidation time t in minutes, for an oxidation in moist oxygen at 1000 ° C.

As noted previously, the oxidation inhibitory activity of implanted nitrogen atoms is much more effective when these ions are implanted through an oxide layer in the immediate vicinity of the oxide-silicon interface than when they are directly in the silicon, or implanted through a thin oxide layer relative to the implantation range. As an example, Figure 18 shows the oxide thickness in µm (for oxidation in moist oxygen) as a function of time in minutes for a nitrogen ion implantation of 55keV at a dose of 5x10 25 N * ions. In addition, curve I represents the case of implantation through a 50 nm thick oxide layer, and curve II represents that of implantation through a 70 nm thick oxide layer.

Finally it is noted that repeated application of the method according to the invention is possible.

For example, Figure 19 shows in cross section the application of overlapping oxidized polycrystalline control electrodes 55 and 56, the electrode 55 being first applied and oxidized in the manner described, after which the second electrode 56 is deposited and patterned over the oxide layer 57, and using at least a portion of the mask used for this patterning as an implantation mask, nitrogen ions 12 are again implanted next to the electrode 56 through the oxide layer 54, followed by thermal oxidation of the 790 2 8 78 13.4.79 13 PHN 9414. electrode 5 ^ 5 10 15 20 25 30 35 790 2 8 78

Claims (12)

1. A method for manufacturing a semiconductor device, in which an insulating layer is applied to the surface of at least a part of a semiconductor region of silicon, on which insulating layer a silicon layer is applied, which layer is applied by means of a masking layer etched in a pattern, after which the exposed surface of the silicon pattern is provided with a silicon oxide layer by thermal oxidation, during which oxidation the silicon region 10 located below the insulating layer is practically not oxidized, characterized in that an insulating layer of silicon oxide is applied and that after the pattern etching of the silicon layer and before the thermal oxidation in the presence of at least a part of the masking layer via the insulating layer, ion implantation 15 is applied to the surface of the silicon region on either side of the silicon pattern, the oxidation-inhibiting ions being applied to the silicon cartridge parts of mask the masking layer against this implantation. 2. Process according to claim 1, characterized in that the oxidation-inhibiting ions are nitrogen ions. Method according to claim 1 or 2, characterized in that the implantation dose and implantation energy are chosen such that the concentration of the implanted oxidation-inhibiting ions at the interface between the insulating 21 layer and the underlying silicon region is at least 10 790 2 8 78 13.4.79 j5 PHN 9414 is 3 atoms per cm. 4. A method according to any one of the preceding claims, characterized in that the oxidation-inhibiting ions are implanted with such energy that the maximum concentration is within a distance of about 20 nm from the interface between the insulating layer and the silicon region. . 5. A method according to any one of the preceding claims, characterized in that the silicon layer is provided with an oxide layer by oxidation before it is etched in pattern. 6. A method according to claim 5, characterized in that, before etching the silicon layer in pattern, the oxide layer is etched away at least a part of its thickness at the location of a contact window to be applied to the silicon pattern to be formed. 7. A method according to any one of the preceding claims, characterized in that the silicon region is provided with an oxide pattern at least partly sunk into the region, which surrounds part of the silicon region, on which part the insulating layer of silicon oxide is applied, and in that the silicon cartridge is partially applied to the sunken oxide cartridge. 8. A method according to any one of the preceding claims, characterized in that contact windows are etched into the insulating layer after the oxidation of the silicon pattern. Method according to claim 8, characterized in that the oxidized silicon pattern is used as an etching mask when etching the contact windows. 9 * N.V. Philips * Incandescent light factories in Eindhoven. 13.4.79 1H PHN 9414 10. Method according to claim 8 or 9, characterized in that the sunken oxide pattern serves as an etching mask during the etching of the contact windows. 11. A method according to any one of claims 8, 9 and 10, characterized in that the silicon cartridge forms the control electrode structure of a field effect transistor with an insulated control electrode, at least part of A method according to any one of claims 1 to 7, characterized in that the silicon pattern forms at least a part of the control electrode structure of a charge-coupled device 790 28 78 13.4.79 / 6 PHN 9414. 5 10 15 20 25 30 7902878 35