JPS6244819B2 - - Google Patents
Info
- Publication number
- JPS6244819B2 JPS6244819B2 JP15854880A JP15854880A JPS6244819B2 JP S6244819 B2 JPS6244819 B2 JP S6244819B2 JP 15854880 A JP15854880 A JP 15854880A JP 15854880 A JP15854880 A JP 15854880A JP S6244819 B2 JPS6244819 B2 JP S6244819B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- gate electrode
- semiconductor
- forming
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 92
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 60
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】
本発明はMOS型半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a MOS type semiconductor device.
従来のMOS型半導体装置ではゲート電極が素
子部上に凸状に形成されていたため、この上にゲ
ート電極を横切つて形成される配線がゲート電極
の段部において断切れを生じるという問題があ
り、またゲート電極は選択エツチングによつて形
成されていたためオーバーハング形状となり、ゲ
ート耐圧の低下をもたらすという問題があつた。 In conventional MOS semiconductor devices, the gate electrode is formed in a convex shape on the element part, so there is a problem in that the wiring formed above and across the gate electrode is broken at the stepped part of the gate electrode. Furthermore, since the gate electrode was formed by selective etching, it had an overhanging shape, which caused a problem of lowering the gate breakdown voltage.
そこでこれらの問題を解決するものとして、１
導電型の半導体基板表面に逆導電型のゲート電極
を埋込形成し、該ゲート電極上に絶縁膜を介して
設置された半導体層にソース領域およびドレイン
領域を形成したMOS型半導体装置が開発されて
いる。このような構造からなるMOS型半導体装
置においては、表面が平坦であり、またエツチン
グによるオーバーハング状のゲート電極形成を回
避できるから、従来構造のMOS型半導体装置に
おける上述の問題は生じない。 Therefore, as a solution to these problems, 1.
A MOS semiconductor device has been developed in which a gate electrode of the opposite conductivity type is buried in the surface of a semiconductor substrate of a conductivity type, and a source region and a drain region are formed in a semiconductor layer placed on the gate electrode with an insulating film interposed therebetween. ing. In a MOS type semiconductor device having such a structure, the surface is flat and formation of an overhanging gate electrode due to etching can be avoided, so that the above-mentioned problems in a MOS type semiconductor device having a conventional structure do not occur.
ところで、上記構造を有するMOS型半導体装
置は従来次のように製造されていた。即ち、１導
電型の半導体基板表面に逆導電型の不純物を選択
拡散してゲート電極を形成し、続いてその上に絶
縁膜を介して、半導体層を形成した後、該半導体
層に導電性を与える不純物を選択拡散してソース
およびドレイン領域を形成する。ところがこの方
法では、ゲート電極形成のための不純物拡散に用
いるマスクと、ソース、ドレインを形成するため
の不純物拡散に用いるマスクとを夫々別に形成し
なければならず、従つて、チヤンネル領域とゲー
ト電極とを自己整合で形成することができない。
その結果、素子の微細化が阻害されるとともに、
ゲート電極とソース、ドレイン領域間の接合容量
が増大して素子の動作速度が低下する原因となつ
ていた。 Incidentally, a MOS type semiconductor device having the above structure has conventionally been manufactured as follows. That is, a gate electrode is formed by selectively diffusing impurities of the opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, and then a semiconductor layer is formed on the gate electrode with an insulating film interposed therebetween. Source and drain regions are formed by selectively diffusing impurities that provide . However, in this method, a mask used for impurity diffusion to form the gate electrode and a mask used for impurity diffusion to form the source and drain must be formed separately, and therefore the channel region and gate electrode must be formed separately. cannot be formed in a self-aligned manner.
As a result, the miniaturization of elements is hindered, and
The junction capacitance between the gate electrode and the source and drain regions increases, causing a reduction in the operating speed of the device.
本発明は上述の事情に鑑みてなされたもので、
ゲート電極を素子領域下に埋込形成した構造の
MOS型半導体装置を製造するに際し、チヤンネ
ル領域とゲート電極とを自己整合的に形成し得る
MOS型半導体装置の製造方法を提供するもので
ある。 The present invention was made in view of the above circumstances, and
The structure has a gate electrode buried under the element area.
When manufacturing MOS type semiconductor devices, channel regions and gate electrodes can be formed in a self-aligned manner.
A method for manufacturing a MOS type semiconductor device is provided.
即ち、本発明によるMOS型半導体装置の製造
方法は、１導電型の半導体基板表面に該基板と逆
導電型を有する第１の半導体層および更に、その
上に絶縁膜を備えた基体を形成する工程と、前記
絶縁膜上に第２の半導体層を形成する工程と、こ
の第２の半導体層のチヤンネル領域予定部上に不
純物のドーピングを阻止する遮蔽膜を形成する工
程と、この遮蔽膜をマスクとして前記第１の半導
体層にそのゲート電極予定部を電気的に分離し得
る物質をイオン注入してゲート電極を形成する工
程と、前記遮蔽膜をマスクとして前記第２の半導
体層に導電性を与える不純物をドーピングして互
いに分離されたソース領域およびドレイン領域を
形成する工程とを具備したことを特徴とするもの
である。 That is, the method for manufacturing a MOS type semiconductor device according to the present invention includes forming on the surface of a semiconductor substrate of one conductivity type a first semiconductor layer having a conductivity type opposite to that of the substrate, and further comprising a base body having an insulating film thereon. a step of forming a second semiconductor layer on the insulating film; a step of forming a shielding film for preventing impurity doping on a portion of the second semiconductor layer where the channel region is to be formed; forming a gate electrode by ion-implanting a substance capable of electrically isolating the intended gate electrode portion of the first semiconductor layer into the first semiconductor layer as a mask; The method is characterized by comprising a step of doping with an impurity that provides a source region and a drain region separated from each other.
本発明における半導体基板および第１の半導体
層としては、Si、Ge、GaAs等の半導体物質から
なるｐ型またはｎ型の半導体基板および半導体層
を用いることができる。ｐ型の半導体基板を用い
た場合には第１の半導体層をｎ型とし、またｎ型
の半導体基板を用いた場合には第１の半導体層を
ｐ型とする。 As the semiconductor substrate and first semiconductor layer in the present invention, a p-type or n-type semiconductor substrate and semiconductor layer made of a semiconductor material such as Si, Ge, or GaAs can be used. When a p-type semiconductor substrate is used, the first semiconductor layer is of n-type, and when an n-type semiconductor substrate is used, the first semiconductor layer is of p-type.
本発明における絶縁膜はMOS型トランジスタ
のゲート絶縁膜となるものであり、従つて、通常
は熱酸化またはCVD法によつて形成された半導
体物質の酸化膜を用いる。 The insulating film in the present invention serves as a gate insulating film of a MOS type transistor, and therefore, an oxide film of a semiconductor material usually formed by thermal oxidation or CVD method is used.
本発明における半導体基板、第１の半導体層お
よび絶縁膜がこの順序で積層された基体を形成す
る方法としては、まず半導体基板上に第１の半導
体層を形成し、続いて該第１の半導体層上に絶縁
膜を形成してもよく、また、半導体基板上に絶縁
膜を形成した後、該絶縁膜を通して半導体基板に
該基板と逆の導電型を与える不純物をイオン注入
し、これを活性化することにより絶縁膜下に第１
の半導体層を形成してもよい。 In the present invention, a method for forming a base body in which a semiconductor substrate, a first semiconductor layer, and an insulating film are stacked in this order includes first forming a first semiconductor layer on a semiconductor substrate, and then forming a first semiconductor layer on a semiconductor substrate. An insulating film may be formed on the semiconductor substrate, and after forming the insulating film on the semiconductor substrate, ions of an impurity that gives the semiconductor substrate a conductivity type opposite to that of the substrate are implanted through the insulating film, and the impurity is activated. The first layer is formed under the insulating film by
A semiconductor layer may be formed.
本発明における第２の半導体層としては、Si、
Ge、GaAs等の半導体物質からなる半導体層を用
いることができる。この第２の半導体層を形成す
る方法として、通常は気相成長法を用いるが、こ
のとき絶縁膜上に形成された第２の半導体層は多
結晶の半導体層となる。第２の半導体層は素子が
形成される半導体層であるから、レーザービーム
等のエネルギービーム照射により単結晶化を行な
い、素子性能の改善を図るのが好ましい。また必
要に応じて適宜チヤンネルドープを行なつてしき
い値電圧（ＶTH）を制御する。 The second semiconductor layer in the present invention includes Si,
A semiconductor layer made of a semiconductor material such as Ge or GaAs can be used. As a method for forming this second semiconductor layer, usually a vapor phase growth method is used, and at this time, the second semiconductor layer formed on the insulating film is a polycrystalline semiconductor layer. Since the second semiconductor layer is a semiconductor layer in which an element is formed, it is preferable to perform single crystallization by irradiation with an energy beam such as a laser beam to improve element performance. Further, channel doping is performed as necessary to control the threshold voltage (V TH ).
本発明における不純物ドーピングを阻止する遮
蔽膜としては、イオン注入に対するマスクとなり
得るものを用いる。このような遮蔽膜としては例
えばフオトレジスト膜あるいはAl、Mo、Ｗ等の
金属膜を用いることができる。この遮蔽膜は光蝕
刻法または光蝕刻法を用いた選択エツチング法に
より、第２の半導体層のチヤンネル領域上に形成
する。 As the shielding film for blocking impurity doping in the present invention, a material that can serve as a mask for ion implantation is used. As such a shielding film, for example, a photoresist film or a metal film such as Al, Mo, W, etc. can be used. This shielding film is formed on the channel region of the second semiconductor layer by a photolithography method or a selective etching method using a photolithography method.
本発明における第１の半導体層のゲート電極予
定部を電気的に分離し得る物質としては、例えば
酸素または窒素等のように第１の半導体層と反応
してこれを絶縁物層に転化する物質、あるいは第
１の半導体層を半導体基板と同導電型に転化し得
る物質を用いる。これ等の物質を前記遮蔽膜をマ
スクとして第１の半導体層にイオン注入すること
により、第１の半導体層のゲート電極予定部のみ
がイオン注入されずに残る。従つて、酸素、窒素
等をイオン注入した場合、その後の熱処理により
第１の半導体層のイオン注入部分が絶縁物層に転
化し、イオン注入されなかつた部分にゲート電極
が形成される。このゲート電極は側方を絶縁物層
によつて絶縁分離され、また逆の導電型を有する
半導体基板とはPN接合によつて分離される。一
方、前記遮蔽膜をマスクとして第１の半導体層を
基板と同導電型に転化し得る物質をイオン注入し
た場合には、その後の活性化によつてイオン注入
部分を基板と同導電型に転化することにより、イ
オン注入されなかつた部分のみが基板とは逆の導
電型で残留し、従つて周囲をPN接合で電気的に
分離されたゲート電極が形成される。しかし、こ
の場合には接合容量が増大して素子の動作速度が
遅くなるから、第１の絶縁物層にイオン注入する
物質としては酸素または窒素等を用い、ゲート電
極以外の第１の半導体層を絶縁物層に転化する方
法がより好ましい。 In the present invention, the substance capable of electrically isolating the gate electrode portion of the first semiconductor layer includes a substance that reacts with the first semiconductor layer and converts it into an insulating layer, such as oxygen or nitrogen. Alternatively, a substance capable of converting the first semiconductor layer into the same conductivity type as the semiconductor substrate is used. By ion-implanting these substances into the first semiconductor layer using the shielding film as a mask, only the portion of the first semiconductor layer where the gate electrode is to be implanted remains without being ion-implanted. Therefore, when ions of oxygen, nitrogen, etc. are implanted, the ion-implanted portion of the first semiconductor layer is converted into an insulating layer by subsequent heat treatment, and a gate electrode is formed in the portion where ions were not implanted. This gate electrode is laterally insulated and separated by an insulating layer, and is separated from a semiconductor substrate having an opposite conductivity type by a PN junction. On the other hand, when a substance capable of converting the first semiconductor layer into the same conductivity type as the substrate is ion-implanted using the shielding film as a mask, the ion-implanted portion is converted into the same conductivity type as the substrate through subsequent activation. By doing so, only the portion that has not been ion-implanted remains with a conductivity type opposite to that of the substrate, thus forming a gate electrode whose surroundings are electrically isolated by a PN junction. However, in this case, the junction capacitance increases and the operating speed of the device slows down, so oxygen or nitrogen is used as the substance to be ion-implanted into the first insulating layer, and the first semiconductor layer other than the gate electrode is More preferred is a method of converting the oxide into an insulating layer.
本発明において、第２の半導体層にソース、ド
レイン領域を形成するための不純物ドーピングの
方法としては、熱拡散法またはイオン注入法を用
いることができる。何れにしても、この不純物ド
ーピングはゲート電極形成のためのイオン注入に
用いたと同じ遮蔽膜をマスクとして行なう。従つ
て、チヤンネル領域はゲート電極に対して自己整
合的に形成される。 In the present invention, a thermal diffusion method or an ion implantation method can be used as an impurity doping method for forming source and drain regions in the second semiconductor layer. In any case, this impurity doping is performed using the same shielding film used for ion implantation for forming the gate electrode as a mask. Therefore, the channel region is formed in self-alignment with the gate electrode.
以下、図面を参照して本発明の１実施例を説明
する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
実施例
〔〕 まず、ｐ型シリコン基板１の表面を熱酸
化して厚さ500ÅのSiO2膜２を成長させる（第
１図々示）。Example [1] First, the surface of a p-type silicon substrate 1 is thermally oxidized to grow a SiO 2 film 2 with a thickness of 500 Å (as shown in the first figure).
〔〕 次に、イオン注入法により加速電圧
100keV、ドーズ量１×1016／cm2の条件下で砒
素をSiO2膜２を通してｐ型基板１表層にドー
プする（第２図々示）。[] Next, the acceleration voltage is increased by ion implantation method.
Arsenic is doped into the surface layer of the p-type substrate 1 through the SiO 2 film 2 under conditions of 100 keV and a dose of 1×10 16 /cm 2 (as shown in the second figure).
〔〕 次に、熱処理を行なつてイオン注入され
た砒素を活性化し、ｐ型シリコン基板１表層に
SiO2膜２と接したｎ型の第１の半導体層３を
形成する。引き続き、CVD法により全面に厚
さ3000Åの多結晶シリコン層を堆積し、更にし
きい値電圧（ＶTH）を制御するためにボロンを
チヤンネルドープした後、熱処理による活性化
を行なつてｐ導電型を有する第２の半導体層４
を形成する（第３図々示）。[]Next, heat treatment is performed to activate the implanted arsenic ions and form them on the surface layer of the p-type silicon substrate 1.
An n-type first semiconductor layer 3 in contact with the SiO 2 film 2 is formed. Subsequently, a polycrystalline silicon layer with a thickness of 3000 Å is deposited on the entire surface by CVD method, and after channel doping with boron to control the threshold voltage (V TH ), activation is performed by heat treatment to make it p-conductive. Second semiconductor layer 4 having a mold
(as shown in the third figure).
〔〕 次に、第２の半導体層４のチヤンネル領
域予定部上に光蝕刻法によりフオトレジスト膜
５を形成した後、これをマスクとして酸素を加
速電圧180keV、ドーズ量１×1018／cm2の条件
でイオン注入する。イオン注入された酸素は第
２の半導体層４およびSiO2膜２を貫通して第
１の半導体層３に達する（第４図々示）。[] Next, after forming a photoresist film 5 on the planned channel region of the second semiconductor layer 4 by photolithography, using this as a mask, oxygen was applied at an acceleration voltage of 180 keV and a dose of 1×10 18 /cm 2 Ion implantation is performed under the following conditions. The ion-implanted oxygen penetrates the second semiconductor layer 4 and the SiO 2 film 2 and reaches the first semiconductor layer 3 (as shown in the fourth figure).
この場合、注入された酸素は第１の半導体層
よりもやや深くまで分布する。 In this case, the implanted oxygen is distributed slightly deeper than the first semiconductor layer.
〔〕 次にフオトレジスト膜５をマスクとして
砒素を加速電圧120keV、ドーズ量１×1016／
cm2の条件で第２の半導体層４にイオン注入す
る。（第５図々示）。[] Next, using the photoresist film 5 as a mask, arsenic was applied at an acceleration voltage of 120 keV and a dose of 1×10 16 /
Ions are implanted into the second semiconductor layer 4 under conditions of cm 2 . (See Figure 5).
〔〕 次に、フオトレジスト膜５を除去した
後、熱処理を施す。これによつて第１の半導体
層の酸素注入部分はSiO2層６に転化され、酸
素が注入されなかつた部分のみがn+型のシリ
コン層として残留し、ゲート電極７が形成され
る。この場合、酸素イオンが第１の半導体層よ
りもやや深くまで分布しているため、SiO2層
６はゲート電極７よりも厚く形成される。一
方、第２の半導体層４の砒素をイオン注入され
た部分はこの熱処理によつて活性化されてn+
型のシリコン層となり、砒素が注入されなかつ
た部分はｐ型のまま残留してチヤンネル領域８
が形成される。続いて第２の半導体層４を選択
エツチングしてソース領域９およびドレイン領
域１０を形成する（第６図々示）。[] Next, after removing the photoresist film 5, heat treatment is performed. As a result, the oxygen-implanted portion of the first semiconductor layer is converted into the SiO 2 layer 6, and only the portion into which oxygen has not been implanted remains as an n + type silicon layer, forming the gate electrode 7. In this case, the SiO 2 layer 6 is formed thicker than the gate electrode 7 because the oxygen ions are distributed slightly deeper than the first semiconductor layer. On the other hand, the part of the second semiconductor layer 4 into which arsenic ions have been implanted is activated by this heat treatment and n +
The part where arsenic is not implanted remains as a p-type silicon layer and becomes a channel region 8.
is formed. Subsequently, the second semiconductor layer 4 is selectively etched to form a source region 9 and a drain region 10 (as shown in FIG. 6).
〔〕 次に、CVD法により厚さ１μｍのSiO2膜
からなる層間絶縁膜１１を堆積し、選択エツチ
ングによりコンタクトホールを開口した後、
Alの蒸着およびパターンニングを行ない、ソ
ース電極１２およびドレイン電極１３等のAl
取出電極を形成してMOS型トランジスタを得
る（第７図々示）。[] Next, an interlayer insulating film 11 made of SiO 2 film with a thickness of 1 μm was deposited by the CVD method, and a contact hole was opened by selective etching.
Evaporation and patterning of Al is performed to form the source electrode 12, drain electrode 13, etc.
A lead electrode is formed to obtain a MOS transistor (as shown in FIG. 7).
このMOS型トランジスタにおいて、n+型の
ゲート電極７に基板に対して正のゲート電圧を
印加すれば、該ゲート電圧はn+型ゲート電極
とｐ型シリコン基板１間のPN接合による逆方
向耐圧によつて維持される。 In this MOS transistor, if a positive gate voltage is applied to the n + type gate electrode 7 with respect to the substrate, the gate voltage will be increased by the reverse breakdown voltage due to the PN junction between the n + type gate electrode and the p type silicon substrate 1. maintained by.
上述の実施例によれば、ゲート電極７を形成
するための酸素のイオン注入とソース、ドレイ
ン領域９，１０を形成するための不純物のイオ
ン注入とを同一のフオトレジスト膜５をマスク
として行なつているため、ゲート電極７とチヤ
ンネル領域８とを自己整合で形成することがで
きる。従つてゲート電極７とソース、ドレイン
領域９，１０との重なりによる接合容量の増大
を回避して、動作速度の遅延を防止することが
できる。また、ゲート電極とソース、ドレイン
領域とを別々のマスクを用いて形成する場合の
ようにマスク合せの誤差を見込んだ余裕をもた
せる必要がないから、素子の微細化を達成する
ことができる。 According to the embodiment described above, oxygen ion implantation for forming the gate electrode 7 and impurity ion implantation for forming the source and drain regions 9 and 10 are performed using the same photoresist film 5 as a mask. Therefore, the gate electrode 7 and the channel region 8 can be formed in self-alignment. Therefore, an increase in junction capacitance due to the overlap between the gate electrode 7 and the source and drain regions 9 and 10 can be avoided, and a delay in operating speed can be prevented. Further, unlike the case where the gate electrode, source, and drain regions are formed using separate masks, there is no need to provide a margin for mask alignment errors, so that miniaturization of the device can be achieved.
なお、上記実施例では第１の半導体層３の活
性化と第２の半導体層４の活性化とを別々の熱
処理によつて行なつているが、第１の半導体層
３を活性化してn+型とするための熱処理はチ
ヤンネルドープした第２の半導体層４を活性化
してｐ導電型とするための熱処理と兼用して行
なうこともできる。 In the above embodiment, the activation of the first semiconductor layer 3 and the activation of the second semiconductor layer 4 are performed by separate heat treatments. The heat treatment for making it + type can also be carried out in combination with the heat treatment for activating the channel-doped second semiconductor layer 4 and making it p conductivity type.
以上詳述したように、本発明によればゲート電
極をチヤンネル領域下の基板に埋込形成した表面
が平坦なMOS型半導体装置を製造するに際し、
ゲート電極とチヤンネル領域とを自己整合的に形
成でき、もつて動作速度の遅延防止および素子の
微細化を達成し得るMOS型半導体装置の製造方
法を提供し得るものである。 As detailed above, according to the present invention, when manufacturing a MOS type semiconductor device with a flat surface in which a gate electrode is embedded in a substrate under a channel region,
It is therefore possible to provide a method for manufacturing a MOS type semiconductor device in which a gate electrode and a channel region can be formed in a self-aligned manner, thereby preventing delays in operating speed and achieving miniaturization of elements.
第１図〜第７図は本発明の１実施例における
MOS型半導体装置の製造工程を示す断面図であ
る。
１……ｐ型シリコン基板、２……SiO2膜、３
……第１の半導体層、４……第２の半導体層、５
……フオトレジスト膜、６……SiO2層、７……
ゲート電極、８……チヤンネル領域、９……ソー
ス領域、１０……ドレイン領域、１１……層間絶
縁膜、１２……ソース電極、１３……ドレイン電
極。
FIGS. 1 to 7 show one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS type semiconductor device. 1...p-type silicon substrate, 2...SiO 2 film, 3
...First semiconductor layer, 4...Second semiconductor layer, 5
...Photoresist film, 6...SiO 2 layer, 7...
Gate electrode, 8... Channel region, 9... Source region, 10... Drain region, 11... Interlayer insulating film, 12... Source electrode, 13... Drain electrode.
Claims (1)
型を有する第１の半導体層および更にその上に絶
縁膜を備えた基体を形成する工程と、前記絶縁膜
上に第２の半導体層を形成する工程と、この第２
の半導体層のチヤンネル領域予定部上に不純物の
ドーピングを阻止する遮蔽膜を形成する工程と、
この遮蔽膜をマスクとして前記第１の半導体層に
そのゲート電極予定部を電気的に分離し得る物質
をイオン注入してゲート電極を形成する工程と、
前記遮蔽膜をマスクとして前記第２の半導体層に
導電性を与える不純物をドーピングして互いに分
離されたソース領域およびドレイン領域を形成す
る工程とを具備したことを特徴とするMOS型半
導体装置の製造方法。 ２ 第１の半導体層のゲート電極予定部を電気的
に分離し得る物質が、第１の半導体層を絶縁物層
に転化し得る物質である特許請求の範囲第１項記
載のMOS型半導体装置の製造方法。 ３ 第１の半導体層のゲート電極予定部を電気的
に分離し得る物質が、第１の半導体層を半導体基
板と同導電型に転化し得る物質であることを特徴
とする特許請求の範囲第１項記載のMOS型半導
体装置の製造方法。[Claims] 1. A step of forming a base body having a first semiconductor layer having a conductivity type opposite to that of the substrate and an insulating film thereon on the surface of a semiconductor substrate of one conductivity type; a step of forming a second semiconductor layer;
forming a shielding film for preventing doping of impurities on the intended channel region of the semiconductor layer;
forming a gate electrode by ion-implanting a substance capable of electrically isolating the intended gate electrode portion of the first semiconductor layer using the shielding film as a mask;
Manufacturing a MOS type semiconductor device, comprising the step of doping the second semiconductor layer with an impurity that imparts conductivity using the shielding film as a mask to form a source region and a drain region separated from each other. Method. 2. The MOS semiconductor device according to claim 1, wherein the substance capable of electrically isolating the gate electrode portion of the first semiconductor layer is a substance capable of converting the first semiconductor layer into an insulating layer. manufacturing method. 3. Claim 1, characterized in that the substance capable of electrically isolating the intended gate electrode portion of the first semiconductor layer is a substance capable of converting the first semiconductor layer into the same conductivity type as the semiconductor substrate. A method for manufacturing a MOS type semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854880A JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854880A JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5783059A JPS5783059A (en) | 1982-05-24 |
| JPS6244819B2 true JPS6244819B2 (en) | 1987-09-22 |
Family
ID=15674108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15854880A Granted JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5783059A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065754B2 (en) * | 1983-03-31 | 1994-01-19 | 富士通株式会社 | Semiconductor device |
| JPH0729320B2 (en) * | 1986-10-31 | 1995-04-05 | 日本ゼオン株式会社 | Reaction injection molding method |
| JPH05211166A (en) * | 1991-12-02 | 1993-08-20 | Nec Corp | Thin film field-effect trasistor |
| WO2001097290A2 (en) * | 2000-06-16 | 2001-12-20 | Advanced Micro Devices, Inc. | Buried inverted gate field-effect transistor (bigfet) |
-
1980
- 1980-11-11 JP JP15854880A patent/JPS5783059A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5783059A (en) | 1982-05-24 |
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