[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Chopra et al., 2018 - Google Patents

A model-based, Bayesian approach to the CF4/Ar etch of SiO2

Chopra et al., 2018

View PDF
Document ID
3960527195035686740
Author
Chopra M
Helpert S
Verma R
Zhang Z
Zhu X
Bonnecaze R
Publication year
Publication venue
Design-Process-Technology Co-optimization for Manufacturability XII

External Links

Snippet

The design and optimization of highly nonlinear and complex processes like plasma etching is challenging and timeconsuming. Significant effort has been devoted to creating plasma profile simulators to facilitate the development of etch recipes. Nevertheless, these …
Continue reading at par.nsf.gov (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]

Similar Documents

Publication Publication Date Title
TWI851237B (en) Non-transitory computer-readable medium, computing device-implemented method for process model calibration, and virtual fabrication system
KR100582969B1 (en) Method and apparatus for predicting surface profile of plasma-treatment
TWI866734B (en) System and method for process window optimization in a virtual semiconductor device fabrication environment
Chopra et al. A model-based, Bayesian approach to the CF4/Ar etch of SiO2
National Research Council et al. Plasma processing of materials: scientific opportunities and technological challenges
Panneerchelvam et al. Trilayer hardmask lithography and etch for BEOL manufacturing
Kuboi Review and future perspective of feature scale profile modeling for high-performance semiconductor devices
Guo et al. Optimizing plasma etching: Integrating precise three-dimensional etching simulation and machine learning for multi-objective optimization
Chopra et al. A method to accelerate creation of plasma etch recipes using physics and Bayesian statistics
Jimenez-Fernandez et al. Prediction of silicon dry etching using a piecewise linear algorithm
Wu et al. Photoresist 3D profile related etch process simulation and its application to full chip etch compact modeling
JP2006518925A (en) Method and system for mechanical modeling and method optimization of semiconductor etching processes
TWI512389B (en) Methods for directed self-assembly process/proximity correction
Constantoudis et al. Line-edge-roughness transfer during plasma etching: modeling approaches and comparison with experimental results
Chopra et al. Rapid recipe formulation for plasma etching of new materials
US10403516B2 (en) Etching characteristic estimation method, program, information processing apparatus, processing apparatus, designing method, and production method
Shao et al. Loading effect during SiGe/Si stack selective isotropic etching for gate-all-around transistors
Ban et al. Fast etch recipe creation with automated model-based process optimization
Dunn et al. Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond
Helpert et al. Simulation and optimization of etch on flexible substrates for roll-to-roll processing
TW200925793A (en) Method for feature prediction, method for manufacturing photomask, method for manufacturing electronic component, and program for feature prediction
Bunday et al. Simulating SEM imaging of via bottoms
Aguinsky et al. Modeling and analysis of sulfur hexafluoride plasma etching for silicon microcavity resonators
Kearney et al. Accelerated optimization of multilayer trench etches using model-based experimental design
Graves et al. DSA graphoepitaxy calibrations for contact hole multiplication