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Wang et al., 2009 - Google Patents

A design of complex square root for FPGA implementation

Wang et al., 2009

Document ID
3118681818665814563
Author
Wang D
Ercegovac M
Publication year
Publication venue
Mathematics for Signal and Information Processing

External Links

Snippet

We present a design for FPGA implementation of a complex square root algorithm for fixed- point operands in radix-4 representation. The design consists of (i) argument prescaling,(ii) residual recurrence, and (iii) result postscaling. These parts share logic resources and …
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Classifications

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    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
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    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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