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Bhardwaj et al., 2014 - Google Patents

Power-and area-efficient approximate wallace tree multiplier for error-resilient systems

Bhardwaj et al., 2014

Document ID
17643060260836544448
Author
Bhardwaj K
Mane P
Henkel J
Publication year
Publication venue
Fifteenth international symposium on quality electronic design

External Links

Snippet

Today in sub-nanometer regime, chip/system designers add accuracy as a new constraint to optimize Latency-Power-Area (LPA) metrics. In this paper, we present a new power and area-efficient Approximate Wallace Tree Multiplier (AWTM) for error-tolerant applications …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F7/52Multiplying; Dividing
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    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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