Bhardwaj et al., 2014 - Google Patents
Power-and area-efficient approximate wallace tree multiplier for error-resilient systemsBhardwaj et al., 2014
- Document ID
- 17643060260836544448
- Author
- Bhardwaj K
- Mane P
- Henkel J
- Publication year
- Publication venue
- Fifteenth international symposium on quality electronic design
External Links
Snippet
Today in sub-nanometer regime, chip/system designers add accuracy as a new constraint to optimize Latency-Power-Area (LPA) metrics. In this paper, we present a new power and area-efficient Approximate Wallace Tree Multiplier (AWTM) for error-tolerant applications …
- 238000004088 simulation 0 abstract description 3
Classifications
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
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- G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
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