Vitkovskiy et al., 2013 - Google Patents
Dynamic fault‐tolerant routing algorithm for networks‐on‐chip based on localised detouring pathsVitkovskiy et al., 2013
View PDF- Document ID
- 15903492711042098411
- Author
- Vitkovskiy A
- Soteriou V
- Nicopoulos C
- Publication year
- Publication venue
- IET Computers & Digital Techniques
External Links
Snippet
Downscaled complementary metal‐oxide semiconductor (CMOS) technology feature sizes have enabled massive transistor integration densities. Multi‐core chips with billions of transistors are now a reality. However, this rapid increase in on‐chip resources has come at …
- 238000005516 engineering process 0 abstract description 16
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/06—Deflection routing, e.g. hot-potato routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network-specific arrangements or communication protocols supporting networked applications
- H04L67/10—Network-specific arrangements or communication protocols supporting networked applications in which an application is distributed across nodes in the network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/48—Routing tree calculation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Aisopos et al. | Ariadne: Agnostic reconfiguration in a disconnected network environment | |
Gabis et al. | NoC routing protocols–objective-based classification | |
Valinataj et al. | A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip | |
Ebrahimi et al. | MAFA: Adaptive fault-tolerant routing algorithm for networks-on-chip | |
Vitkovskiy et al. | Dynamic fault‐tolerant routing algorithm for networks‐on‐chip based on localised detouring paths | |
Ahmed et al. | Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems | |
Pasricha et al. | NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults | |
Vitkovskiy et al. | A dynamically adjusting gracefully degrading link-level fault-tolerant mechanism for NoCs | |
Iordanou et al. | Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips | |
Ganguly et al. | A denial-of-service resilient wireless NoC architecture | |
Mak et al. | Embedded transitive closure network for runtime deadlock detection in networks-on-chip | |
Daneshtalab et al. | A generic adaptive path-based routing method for MPSoCs | |
Joshi et al. | Genetic algorithm-and cuckoo search algorithm-based routing optimizations in network-on-chip | |
Pasricha et al. | OE+ IOE: A novel turn model based fault tolerant routing scheme for networks-on-chip | |
Taheri et al. | ON–OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs | |
Yang et al. | Dodec: Random-link, low-radix on-chip networks | |
Arun et al. | A novel energy efficient multicasting approach for mesh NoCs | |
Sleeba et al. | Energy‐efficient fault tolerant technique for deflection routers in two‐dimensional mesh Network‐on‐Chips | |
Silveira et al. | Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs | |
Manzoor et al. | Prime turn model and first last turn model: an adaptive deadlock free routing for network-on-chips | |
Meena et al. | A new recursive partitioning multicast routing algorithm for 3D network-on-chip | |
Vitkovskiy et al. | A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting | |
Afsharpour et al. | Performance/energy aware task migration algorithm for many‐core chips | |
Bishnoi et al. | Resilient routing implementation in 2D mesh NoC | |
Zinzuwadia et al. | An efficient deadlock-free NARCO based fault tolerant routing algorithm in NoC architecture |