Ramanarayanan et al., 2002 - Google Patents
Characterizing dynamic and leakage power behavior in flip-flopsRamanarayanan et al., 2002
View PDF- Document ID
- 15733268428975469842
- Author
- Ramanarayanan R
- Vijaykrishnan N
- Irwin M
- Publication year
- Publication venue
- 15th Annual IEEE International ASIC/SOC Conference
External Links
Snippet
This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, 1 V CMOS technology. First, we perform a detailed …
- 238000010192 crystallographic characterization 0 abstract description 13
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Markovic et al. | Analysis and design of low-energy flip-flops | |
Teh et al. | Conditional data mapping flip-flops for low-power and high-performance systems | |
Consoli et al. | Conditional push-pull pulsed latches with 726fJ· ps energy-delay product in 65nm CMOS | |
Ramanarayanan et al. | Characterizing dynamic and leakage power behavior in flip-flops | |
Oskuii | Comparative study on low-power high-performance flip-flops | |
Stojanovic et al. | A unified approach in the analysis of latches and flip-flops for low-power systems | |
Mahmoodi-Meimand et al. | Self-precharging flip-flop (SPFF): A new level converting flip-flop | |
Saini et al. | An Improved Power Gating Technique with Data Retention and Clock Gating | |
Dhong et al. | A 0.42 V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC | |
Elgamel et al. | Noise tolerant low power dynamic TSPCL D flip-flops | |
Xia et al. | Differential CMOS edge-triggered flip-flop with clock-gating | |
Sayed et al. | Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design | |
Venkatraman et al. | A robust, fast pulsed flip-flop design | |
Yu et al. | Dual edge-triggered d-type flip-flop with low power consumption | |
Zyuban et al. | Clocking strategies and scannable latches for low power appliacations | |
Verma et al. | Unleashing Power Efficiency: A Study Comparing Pulsed Latches and Flip-Flops for Low-Power Applications | |
Sayed et al. | A new low power high performance flip-flop | |
Vesterbacka | A robust differential scan flip-flop | |
Krishna et al. | Design and Analysis of 18T Master-Slave Flip-Flop Circuit | |
Zhang et al. | Design of a new sense amplifier flip-flop with improved power-delay-product | |
Bhuvana et al. | A Survey on sequential elements for low power clocking system | |
Mangawati et al. | Clock Gating Integration Using 18T-TSPC Clocked Flip Flop | |
Singh et al. | Design and analysis of clocked subsystem elements using leakage reduction technique | |
Maheshwari | A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops | |
TWI389457B (en) | Double trigger logic circuit |