Lee et al., 2016 - Google Patents
An agile approach to building RISC-V microprocessorsLee et al., 2016
View PDF- Document ID
- 15653359574456055881
- Author
- Lee Y
- Waterman A
- Cook H
- Zimmer B
- Keller B
- Puggelli A
- Kwak J
- Jevtic R
- Bailey S
- Blagojevic M
- Chiu P
- Avizienis R
- Richards B
- Bachrach J
- Patterson D
- Alon E
- Nikolic B
- Asanovic K
- Publication year
- Publication venue
- ieee Micro
External Links
Snippet
The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to …
- 238000000034 method 0 abstract description 53
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/04—CAD in a network environment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Lee et al. | An agile approach to building RISC-V microprocessors | |
Amid et al. | Chipyard: Integrated design, simulation, and implementation framework for custom socs | |
Izraelevitz et al. | Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations | |
Carloni | The case for embedded scalable platforms | |
Gajski et al. | Guest editors' introduction: New VLSI tools | |
Jozwiak et al. | ASAM: automatic architecture synthesis and application mapping | |
Kranenburg et al. | MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture | |
Wang et al. | A methodology for reusable physical design | |
Schmidt et al. | An eight-core 1.44-GHz RISC-V vector processor in 16-nm FinFET | |
Aporva et al. | Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm | |
Chakravarthi et al. | System on Chip (SOC) Architecture: A Practical Approach | |
Smith | Updates of the ITRS design cost and power models | |
Kerrigan et al. | Computer architectures to close the loop in real-time optimization | |
Amid et al. | Chipyard-An integrated SoC research and implementation environment | |
Rykunov | Design of asynchronous microprocessor for power proportionality | |
Pedre et al. | A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA | |
US11657205B2 (en) | Construction, modeling, and mapping of multi-output cells | |
Baungarten-Leon et al. | The Genesis of AI by AI Integrated Circuit: Where AI Creates AI | |
Nepomnyashchy et al. | High-Level Design Flows for VLSI Circuit | |
Hari et al. | Automatic constraint based test generation for behavioral HDL models | |
Economakos et al. | Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies | |
Magyar | Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading | |
Madariaga et al. | Review of electronic design automation tools for high-level synthesis | |
Fernandez-Alvarez et al. | FPGA-based HW/SW co-simulation system for mixed-signal circuits | |
Choudhary | FabScalar: Automating the design of superscalar processors |