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Lee et al., 2016 - Google Patents

An agile approach to building RISC-V microprocessors

Lee et al., 2016

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Document ID
15653359574456055881
Author
Lee Y
Waterman A
Cook H
Zimmer B
Keller B
Puggelli A
Kwak J
Jevtic R
Bailey S
Blagojevic M
Chiu P
Avizienis R
Richards B
Bachrach J
Patterson D
Alon E
Nikolic B
Asanovic K
Publication year
Publication venue
ieee Micro

External Links

Snippet

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to …
Continue reading at people.eecs.berkeley.edu (PDF) (other versions)

Classifications

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    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
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    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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