Pedre et al., 2012 - Google Patents
A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGAPedre et al., 2012
View PDF- Document ID
- 16159831342817166162
- Author
- Pedre S
- Krajník T
- Todorovich E
- Borensztejn P
- Publication year
- Publication venue
- 2012 VIII Southern Conference on Programmable Logic
External Links
Snippet
In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and …
- 238000000034 method 0 title abstract description 46
Classifications
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- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
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