Choi et al., 2024 - Google Patents
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory InterfacesChoi et al., 2024
- Document ID
- 15312252198052653309
- Author
- Choi Y
- Sim C
- Choi J
- Sim J
- Park H
- Kwon Y
- Park S
- Kim S
- Kim C
- Publication year
- Publication venue
- IEEE Transactions on Circuits and Systems I: Regular Papers
External Links
Snippet
This paper presents a 25-Gb/s single-ended four-level pulse amplitude modulation (PAM-4) transmitter (TX) with an integrated pulse width modulation (iPWM)-based feed-forward equalizer (FFE) and a ratio of level mismatch (RLM)-matched voltage-mode driver for high …
- 238000005516 engineering process 0 abstract description 5
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03343—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
- H04L25/0286—Provision of wave shaping within the driver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
- H04L25/03878—Line equalisers; line build-out devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults; Receiver end arrangements for detecting or overcoming line faults
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels; Baseband coding techniques specific to data transmission systems
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/01—Equalisers
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Jeong et al. | A 0.64-pJ/bit 28-Gb/s/pin high-linearity single-ended PAM-4 transmitter with an impedance-matched driver and three-point ZQ calibration for memory interface | |
Roshan-Zamir et al. | A reconfigurable 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65-nm CMOS | |
Park et al. | 30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links | |
Bassi et al. | A high-swing 45 Gb/s hybrid voltage and current-mode PAM-4 transmitter in 28 nm CMOS FDSOI | |
Zheng et al. | A 40-Gb/s quarter-rate SerDes transmitter and receiver chipset in 65-nm CMOS | |
Lee et al. | An 80 mV-swing single-ended duobinary transceiver with a TIA RX termination for the point-to-point DRAM interface | |
Hyun et al. | A 20Gb/s dual-mode PAM4/NRZ single-ended transmitter with RLM compensation | |
Chae et al. | A 12.8-Gb/s quarter-rate transmitter using a 4: 1 overlapped multiplexing driver combined with an adaptive clock phase aligner | |
Chae et al. | A 10.4-Gb/s 1-tap decision feedback equalizer with different pull-up and pull-down tap weights for asymmetric memory interfaces | |
Chae et al. | Data-dependent selection of amplitude and phase equalization in a quarter-rate transmitter for memory interfaces | |
Seo et al. | A 7.8-Gb/s 2.9-pJ/b single-ended receiver with 20-tap DFE for highly reflective channels | |
Kwon et al. | A 33-Gb/s/Pin 1.09-pJ/bit single-ended PAM-3 transceiver with ground-referenced signaling and time-domain decision technique for multi-chip module memory interfaces | |
Kim et al. | A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-coupled equalizer and a voltage offset generator | |
Kang et al. | A 21-Gb/s duobinary transceiver for GDDR interfaces with an adaptive equalizer | |
Kwon et al. | A 15 Gb/s non-return-to-zero transmitter with 1-tap pre-emphasis feed-forward equalizer for low-power ground terminated memory interfaces | |
Fan et al. | A 40-Gb/s PAM-4 transmitter using a 0.16-pJ/bit SST-CML-hybrid (SCH) output driver and a hybrid-path 3-Tap FFE scheme in 28-nm CMOS | |
Su et al. | A 5 Gb/s voltage-mode transmitter using adaptive time-based de-emphasis | |
Chiu et al. | A 32Gb/s time-based PAM-4 transceiver for high-speed DRAM interfaces with in-situ channel loss and bit-error-rate monitors | |
Bae et al. | A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients | |
Lee et al. | A single-ended parallel transceiver with four-bit four-wire four-level balanced coding for the point-to-point dram interface | |
Choi et al. | A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces | |
Lee et al. | A low-power DRAM transmitter with phase and current-mode amplitude equalization to improve impedance matching | |
Choi et al. | A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces | |
Jeong et al. | A 10 Gb/s/pin single-ended transmitter with reflection-aided duobinary modulation for dual-rank mobile memory interfaces | |
Jeong et al. | A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces |