[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Balasubramanian et al., 2007 - Google Patents

Effects of random dopant fluctuations (RDF) on the single event vulnerability of 90 and 65 nm CMOS technologies

Balasubramanian et al., 2007

Document ID
13328796345596298816
Author
Balasubramanian A
Fleming P
Bhuva B
Amusan O
Massengill L
Publication year
Publication venue
IEEE Transactions on Nuclear Science

External Links

Snippet

Random dopant fluctuation (RDF) induced threshold voltage variations affect two critical parameters used as a measure of single event (SE) hardness (i) single event transient (SET) pulse widths and (ii) critical charge. This causes an increase in the spread of SET pulse …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125Cells incorporating circuit means for protection against loss of information
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
Huang et al. A high performance SEU tolerant latch
Zhou et al. Gate sizing to radiation harden combinational logic
Kang et al. Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
Naseer et al. Critical charge characterization for soft error rate modeling in 90nm SRAM
Garg Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations
Maheshwari et al. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
Ahlbin et al. Effect of multiple-transistor charge collection on single-event transient pulse widths
Rossi et al. Impact of bias temperature instability on soft error susceptibility
Cannon et al. The impact of aging effects and manufacturing variation on SRAM soft-error rate
Yibai et al. Impact of circuit placement on single event transients in 65 nm bulk CMOS technology
Samandari-Rad et al. Confronting the variability issues affecting the performance of next-generation SRAM design to optimize and predict the speed and yield
Balasubramanian et al. Effects of random dopant fluctuations (RDF) on the single event vulnerability of 90 and 65 nm CMOS technologies
Xiong et al. Single-Event Upset Cross-Section Trends for D-FFs at the 5-and 7-nm Bulk FinFET Technology Nodes
Du et al. A layout-level approach to evaluate and mitigate the sensitive areas of multiple SETs in combinational circuits
Yankang et al. Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells
Harrington et al. Empirical modeling of FinFET SEU cross sections across supply voltage
Mukhopadhyay et al. Reduction of parametric failures in sub-100-nm SRAM array using body bias
Royer et al. Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm
Cao et al. SE response of guard-gate FF in 16-and 7-nm bulk FinFET technologies
Uemura et al. Neutron-induced soft-error simulation technology for logic circuits
Oliveira et al. Soft Error Impact on FinFET and CMOS XOR Logic Gates
Kou et al. Impact of process variations on reliability and performance of 32-nm 6T SRAM at near threshold voltage
Brendler et al. Evaluating the impact of process variability and radiation effects on different transistor arrangements
Garg et al. 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit
Asenov et al. Combining process and statistical variability in the evaluation of the effectiveness of corners in digital circuit parametric yield analysis