[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Donato et al., 2019 - Google Patents

Memti: Optimizing on-chip nonvolatile storage for visual multitask inference at the edge

Donato et al., 2019

View PDF
Document ID
12143156401132297443
Author
Donato M
Pentecost L
Brooks D
Wei G
Publication year
Publication venue
IEEE Micro

External Links

Snippet

The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several …
Continue reading at discovery.ucl.ac.uk (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models
    • G06N3/02—Computer systems based on biological models using neural network models
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme

Similar Documents

Publication Publication Date Title
Verma et al. In-memory computing: Advances and prospects
Koppula et al. EDEN: Enabling energy-efficient, high-performance deep neural network inference using approximate DRAM
US11625584B2 (en) Reconfigurable memory compression techniques for deep neural networks
Donato et al. Memti: Optimizing on-chip nonvolatile storage for visual multitask inference at the edge
US10346347B2 (en) Field-programmable crossbar array for reconfigurable computing
Prabhu et al. CHIMERA: A 0.92-TOPS, 2.2-TOPS/W edge AI accelerator with 2-MByte on-chip foundry resistive RAM for efficient training and inference
Pentecost et al. Maxnvm: Maximizing dnn storage density and inference efficiency with sparse encoding and error mitigation
Li et al. RRAM-DNN: An RRAM and model-compression empowered all-weights-on-chip DNN accelerator
WO2020117348A2 (en) Non-volatile memory die with deep learning neural network
US20200184335A1 (en) Non-volatile memory die with deep learning neural network
US11074498B2 (en) Static and dynamic precision adaptation for hardware learning and classification
Park et al. Flash-Cosmos: In-flash bulk bitwise operations using inherent computation capability of nand flash memory
US20210089272A1 (en) Ternary in-memory accelerator
Luo et al. AILC: Accelerate on-chip incremental learning with compute-in-memory technology
Soliman et al. Felix: A ferroelectric fet based low power mixed-signal in-memory architecture for dnn acceleration
CN113841165A (en) System and method for training artificial neural networks
Agrawal et al. CASH-RAM: Enabling in-memory computations for edge inference using charge accumulation and sharing in standard 8T-SRAM arrays
Tsai et al. RePIM: Joint exploitation of activation and weight repetitions for in-ReRAM DNN acceleration
Tang et al. Scaling up in-memory-computing classifiers via boosted feature subsets in banked architectures
Luo et al. Codg-reram: An algorithm-hardware co-design to accelerate semi-structured gnns on reram
Sie et al. MARS: Multimacro architecture SRAM CIM-based accelerator with co-designed compressed neural networks
Song et al. STT-RAM buffer design for precision-tunable general-purpose neural network accelerator
Jasemi et al. Reliable and energy efficient MLC STT-RAM buffer for CNN accelerators
Liu et al. Era-bs: Boosting the efficiency of reram-based pim accelerator with fine-grained bit-level sparsity
KR20240046492A (en) Sparsity-aware in-memory computing