[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Zhou et al., 2000 - Google Patents

Optimal low powerX OR gate decomposition

Zhou et al., 2000

View PDF
Document ID
10829386153342304312
Author
Zhou H
Wong D
Publication year
Publication venue
Proceedings of the 37th Annual Design Automation Conference

External Links

Snippet

With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low power decomposition of an XOR gate, if the implementation …
Continue reading at dl.acm.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models

Similar Documents

Publication Publication Date Title
US8595671B2 (en) Low-power FPGA circuits and methods
Roy et al. Circuit activity based logic synthesis for low power reliable operations
US6529861B1 (en) Power consumption reduction for domino circuits
Zhou et al. Optimal low powerX OR gate decomposition
Singh et al. Multi-bit pulsed-latch based low power synchronous circuit design
Yeh et al. Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
Khokha et al. Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique
Chen et al. Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Hiremath et al. Design of low power standard cells using full swing gate diffusion input
Ramalingam et al. Wakeup scheduling in MTCMOS circuits using successive relaxation to minimize ground bounce
Balasubramanian et al. A set theory based factoring technique and its use for low power logic design
Pasandi et al. Depth-bounded graph partitioning algorithm and dual clocking method for realization of superconducting SFQ circuits
Murugasami et al. Performance analysis of clock pulse generators and design of low power area efficient shift register using multiplexer based clock pulse generator
Sasamal et al. Design of Registers and Memory in QCA
Purohit et al. New performance/power/area efficient, reliable full adder design
Willingham et al. Asynchronous, quasi-adiabatic (Asynchrobatic) logic for low-power very wide data width applications
Barkalov et al. Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review
Gonul et al. Design Automation for Charge Recovery Logic
Chandrakar et al. A SAT-based methodology for effective clock gating for power minimization
Ogunti et al. Design of a low power binary counter using bistable storage element
Nayan et al. A review on modified gate diffusion input logic: an approach for area and power efficient digital system design
Praghash et al. Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions
Chrzanowska-Jeske et al. Disjunctive decomposition of switching functions using symmetry information
Aezinia et al. Optimizing high speed flip-flop using genetic algorithm
Mongiya et al. A Review on Designing of Power and Delay Efficient 10T and 14T SRAM Cell