[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Päivänsäde, 2016 - Google Patents

Dynamic power estimation with a hardware emulation acquired switching activity model

Päivänsäde, 2016

View PDF
Document ID
10427286332173620084
Author
Päivänsäde V
Publication year

External Links

Snippet

This thesis is a study of dynamic power estimation at register-transfer level using an activity model acquired with a hardware emulator. The thesis consists of a practical part that presents the studied flow and the testing work related to it and a theory part that supports the …
Continue reading at oulurepo.oulu.fi (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5018Computer-aided design using simulation using finite difference methods or finite element methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/84Timing analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/62Clock network
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Shang et al. Dynamic power consumption in Virtex™-II FPGA family
Xie et al. Performance comparisons between 7-nm FinFET and conventional bulk CMOS standard cell libraries
Datta et al. Modeling and circuit synthesis for independently controlled double gate FinFET devices
Kong et al. Digital timing macromodeling for VLSI design verification
Sanyal et al. An efficient technique for leakage current estimation in nanoscaled CMOS circuits incorporating self-loading effects
Päivänsäde Dynamic power estimation with a hardware emulation acquired switching activity model
Monteiro et al. Power analysis and optimization from circuit to register-transfer levels
Kommuru et al. ASIC design flow tutorial using synopsys tools
Yuan et al. Standard cell library characterization for FinFET transistors using BSIM-CMG models
Vaidyanathan et al. Improving energy efficiency of low-voltage logic by technology-driven design
Nesset Rtl power estimation flow and its use in power optimization
Haataja Register-transfer level power estimation and reduction methodologies of digital system-on-chip building blocks
Rastogi et al. An efficient technique for leakage current estimation in sub 65nm scaled CMOS circuits based on loading effect
Mehra et al. Synopsys Low-Power Design Flow
Xu et al. Average leakage current macromodeling for dual-threshold voltage circuits
Nagel et al. Is SPICE good enough for tomorrow's analog?
Chen et al. Finite-point-based transistor model: A new approach to fast circuit simulation
Garyfallou Novel techniques for timing analysis of VLSI circuits in advanced technology nodes
Vladimirescu The Synergy SPICE–Compact Models
He et al. Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits
Λιλίτσης Power analysis engine implementation for VLSI digital systems
Alexander Simulation based power estimation for digital CMOS technologies
Messaris et al. An evaluation of the equivalent inverter modeling approach
Jain et al. A closed-form energy model for VLSI circuits under wide voltage scaling
Balakrishnan An Experimental Study of the Accuracy of Multiple Power Estimation Methods