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Yu et al., 2009 - Google Patents

Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D packages

Yu et al., 2009

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Document ID
9601926143157380429
Author
Yu A
Khan N
Archit G
Pinjala D
Toh K
Kripesh V
Yoon S
Lau J
Publication year
Publication venue
Ieee transactions on components and packaging technologies

External Links

Snippet

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer …
Continue reading at www.researchgate.net (PDF) (other versions)

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