[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Smutzer et al., 2016 - Google Patents

Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs

Smutzer et al., 2016

Document ID
7815322025771165587
Author
Smutzer C
Degerstrom M
Gilbert B
Publication year
Publication venue
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI)

External Links

Snippet

Demanding signal-and power-integrity performance requirements in high-performance computing (HPC) systems require careful trade-space analysis when prioritizing layer allocations in printed circuit board (PCB) designs. Typically, the topmost layers in a stackup …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, and noise or electromagnetic interference
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Similar Documents

Publication Publication Date Title
TWI705548B (en) Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices
JP2007116179A (en) Package having array of embedded capacitors for power transfer and decoupling of high-speed input/output circuit, and method of manufacturing same
TWI721047B (en) Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices
Deutsch et al. Frequency-dependent losses on high-performance interconnections
Gu et al. High-density silicon carrier transmission line design for chip-to-chip interconnects
Zhao et al. System level power integrity analysis with physics-based modeling methodology
Kam et al. 40-Gb/s package design using wire-bonded plastic ball grid array
Pak et al. Modeling and measurement of radiated field emission from a power/ground plane cavity edge excited by a through-hole signal via based on a balanced TLM and via coupling model
Smutzer et al. Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs
CN113727513B (en) Package substrate, printed circuit board, package device, and electronic apparatus
Muthana et al. Improvements in noise suppression for I/O circuits using embedded planar capacitors
Shiue et al. Reduction in reflections and ground bounce for signal line over slotted power plane using differential coupled microstrip lines
Beyene et al. Signal and power integrity analysis of high-speed links with silicon interposer
JP2005101587A (en) Parallel wiring and integrated circuit
Knighten et al. PDN Design Strategies: III. Planes and materials–are they important factors in power bus design?
Curran et al. The impacts of dimensions and return current path geometry on coupling in single ended through silicon vias
Zhao et al. A novel Z-directed embedded component for the reduction of voltage ripple on the power distribution network for PCBs
Shringarpure et al. Effect of narrow power fills on PCB PDN noise
Smutzer et al. Practical limitations of state-of-the-art passive printed circuit board power delivery networks for high performance compute systems
Budell et al. Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16/spl mu/m CMOS test chip
Di Febo et al. Impact of planar electromagnetic band-gap structures on IR-DROP and signal integrity in high speed printed circuit boards
Liu Quilt packaging: A novel high speed chip-to-chip communication paradigm for system-in-package
Zhu Physics-based equivalent circuit model extraction for system level PDN and a novel PDN impedance measurement method
Chen et al. Overcoming Design Challenges for High Bandwidth Memory Interface with CoWoS
Bai et al. Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk