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Bryant et al., 1983 - Google Patents

Simulator for MOS Digital Systems

Bryant et al., 1983

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Document ID
6058206249061497172
Author
Bryant R
Model S
Publication year
Publication venue
California Institute of Technology, Pasadena, CA

External Links

Snippet

The switch-level model describes the 1ogical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor" switches" with each node having a state 0, 1, or X (for invalid …
Continue reading at authors.library.caltech.edu (PDF) (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
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    • G06F17/504—Formal methods
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    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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