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Jafarof, 2024 - Google Patents

Advancing VTR flow: Integrating ABC9 via Yosys for enhanced technology mapping and optimization

Jafarof, 2024

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Document ID
5873835608057527408
Author
Jafarof N
Publication year

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Snippet

This thesis delves into optimizing the Verilog-to-Routing (VTR) flow, which is crucial in open- source Computer-Aided Design and Field-Programmable Gate Array (FPGA) architecture research. It utilizes ODIN II and Parmys for synthesis, ABC for technology mapping, and …
Continue reading at unbscholar.lib.unb.ca (PDF) (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
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    • G06F17/5086—Mechanical design, e.g. parametric or variational design
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