[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Jiao et al., 2012 - Google Patents

Design, modeling, and test of a programmable adaptive phase-shifting PLL for enhancing clock data compensation

Jiao et al., 2012

View PDF
Document ID
5284134962133060350
Author
Jiao D
Kim B
Kim C
Publication year
Publication venue
IEEE journal of solid-state circuits

External Links

Snippet

Timing compensation between the clock period and datapath delay in the presence of resonant supply noise has drawn a great deal of attention from the circuit design community. This effect, which is often referred to as the clock data compensation effect, manifests itself …
Continue reading at people.ece.umn.edu (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation

Similar Documents

Publication Publication Date Title
Heydari Analysis of the PLL jitter due to power/ground and substrate noise
Bae et al. A 7.6 mW, 414 fs RMS-jitter 10 GHz phase-locked loop for a 40 Gb/s serial link transmitter based on a two-stage ring oscillator in 65 nm CMOS
Ye et al. A multiple-crystal interface PLL with VCO realignment to reduce phase noise
Chan et al. Uniform-phase uniform-amplitude resonant-load global clock distributions
Bowman et al. A 22 nm all-digital dynamically adaptive clock distribution for supply voltage droop tolerance
Bowman et al. A 16 nm all-digital auto-calibrating adaptive clock distribution for supply voltage droop tolerance across a wide operating range
Boulghassoul et al. Towards SET mitigation in RF digital PLLs: From error characterization to radiation hardening considerations
Kang et al. On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures
Jiao et al. Design, modeling, and test of a programmable adaptive phase-shifting PLL for enhancing clock data compensation
US6868534B2 (en) Circuit modeling
Kim et al. Spread spectrum clock generator with delay cell array to reduce electromagnetic interference
Kim et al. A supply-noise sensitivity tracking PLL in 32 nm SOI featuring a deep trench capacitor based loop filter
Gu et al. On-chip supply noise regulation using a low-power digital switched decoupling capacitor circuit
Jiao et al. Circuit design and modeling techniques for enhancing the clock-data compensation effect under resonant supply noise
Jiao et al. A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise
Ravezzi et al. Clock and synchronization networks for a 3 GHz 64 Bit ARMv8 8-core SoC
Bhowmik et al. Clock jitter reduction and flat frequency generation in PLL using autogenerated control feedback
Lee et al. Supply noise insensitive PLL design through PWL behavioral modeling and simulation
Machado et al. Voltage noise analysis with ring oscillator clocks
Machado et al. Robustness to voltage noise with ring oscillator clocks
Blunno et al. Designing low electro magnetic emissions circuits through clock skew optimization
Jiao et al. Enhancing beneficial jitter using phase-shifted clock distribution
Jiao et al. Circuit techniques for enhancing the clock data compensation effect under resonant supply noise
Zhenyu et al. Modeling and analysis of single-event transients in charge pumps
Jiao Circuit modeling and design techniques for efficient power delivery under resonant supply noise