Kang et al., 2015 - Google Patents
Complementary spintronic logic with spin Hall effect-driven magnetic tunnel junctionKang et al., 2015
- Document ID
- 4038364893013643261
- Author
- Kang W
- Zheng C
- Zhang Y
- Ravelosona D
- Lv W
- Zhao W
- Publication year
- Publication venue
- IEEE Transactions on Magnetics
External Links
Snippet
The conventional CMOS transistors reach its power wall due to the increasing leakage current as technology scales down. The spintronic devices show a great promise as one of the alternatives to replace CMOS technology for the next-generation low-power integrated …
- 230000005291 magnetic 0 title abstract description 13
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements using thin films in plane structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L43/00—Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
- H01L43/02—Details
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Guo et al. | Spintronics for energy-efficient computing: An overview and outlook | |
Kang et al. | Modeling and exploration of the voltage-controlled magnetic anisotropy effect for the next-generation low-power and high-speed MRAM applications | |
Zhao et al. | Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit | |
Jabeur et al. | Spin orbit torque non-volatile flip-flop for high speed and low energy applications | |
Roohi et al. | A tunable majority gate-based full adder using current-induced domain wall nanomagnets | |
Zhang et al. | Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions | |
Lakys et al. | Self-enabled “error-free” switching circuit for spin transfer torque MRAM and logic | |
Zhao et al. | Spin-MTJ based non-volatile flip-flop | |
Kang et al. | Spintronic logic design methodology based on spin Hall effect–driven magnetic tunnel junctions | |
Kang et al. | Low store power high-speed high-density nonvolatile SRAM design with spin Hall effect-driven magnetic tunnel junctions | |
Deng et al. | Synchronous 8-bit non-volatile full-adder based on spin transfer torque magnetic tunnel junction | |
Kang et al. | High-speed, low-power, magnetic non-volatile flip-flop with voltage-controlled, magnetic anisotropy assistance | |
KR102378050B1 (en) | Non-volatile data retention circuit, data retention system and method thereof | |
Deng et al. | High-frequency low-power magnetic full-adder based on magnetic tunnel junction with spin-hall assistance | |
Deng et al. | Design optimization and analysis of multicontext STT-MTJ/CMOS logic circuits | |
Deng et al. | Robust magnetic full-adder with voltage sensing 2T/2MTJ cell | |
Zhang et al. | Reliability-enhanced hybrid CMOS/MTJ logic circuit architecture | |
Ben-Romdhane et al. | Design and analysis of racetrack memory based on magnetic domain wall motion in nanowires | |
Zhang et al. | Reliability-enhanced separated pre-charge sensing amplifier for hybrid CMOS/MTJ logic circuits | |
Amirany et al. | High-performance and soft error immune spintronic retention latch for highly reliable processors | |
Jovanović et al. | Comparative analysis of MTJ/CMOS hybrid cells based on TAS and in-plane STT magnetic tunnel junctions | |
Lee et al. | A word line pulse circuit technique for reliable magnetoelectric random access memory | |
Kang et al. | Complementary spintronic logic with spin Hall effect-driven magnetic tunnel junction | |
Barla et al. | Fully nonvolatile hybrid full adder based on SHE+ STT-MTJ/CMOS LIM architecture | |
Parveen et al. | IMCS2: Novel device-to-architecture co-design for low-power in-memory computing platform using coterminous spin switch |