verilog

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

eda verilog vlsi cadence skywater

Updated Jul 25, 2023
Tcl

icglue / icglue

Star

A Tcl-Library for scripted HDL generation

verilog systemverilog hdl verilog-hdl systemverilog-hdl tcl-applications

Updated Apr 30, 2024
Tcl

LSC-Unicamp / processor-ci-controller

Star

Controller module for RISC-V core CI/CD

fpga riscv verilog

Updated Apr 14, 2025
Tcl

Choaib-ELMADI / fpga-programming-for-beginners

Star

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

embedded fpga electronics vhdl embedded-systems verilog systemverilog fpga-soc fpga-board fpga-programming

Updated Aug 25, 2024
Tcl

kkiningh / synthesis-example

Star

Example of a full DC synthesis script for a simple design

verilog synthesis synopsys vlsi designcompiler

Updated Feb 25, 2019
Tcl

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Star

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

Updated Dec 7, 2022
Tcl

timothystotts / fpga-serial-acl-tester-3

Star

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

fpga vhdl verilog systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

yunusesergun / yesergun.fpga.dev

Star

All about FPGA...

fpga clock vhdl rtl verilog vivado axi4-protocol

Updated Apr 26, 2025
Tcl

avinashy2j / StaticTimingAnalysis

Star

Implementation of Timing Exceptions in RTL design for STA

asic verilog tcl-scripts

Updated Sep 15, 2019
Tcl

suoglu / Divider

Star

Hardware integer divider module

fpga hardware verilog divider

Updated Aug 3, 2023
Tcl

RomeoMe5 / FPGA-Matrix-Base-operations

Star

Matrix base operations on FPGA example

fpga verilog hse modelsim miem matrix-operations

Updated May 24, 2019
Tcl

marplyn / Processor-Systems-Architecture

Star

МИЭТ, курс "Архитектуры процессорных систем"

vhdl verilog fgpa

Updated Dec 26, 2022
Tcl

Unicamp-Odhin / PDM_Microphone

Star

PDM Microphone peripheral written in SystemVerilog HDL

audio verilog systemverilog audio-processing pdm

Updated May 3, 2025
Tcl

Bucknalla / warc_fusesoc

Star

WARC Open Fusesoc Cores Repository

hls ip verilog migen open-cores

Updated Mar 17, 2020
Tcl

hummingbird-12 / soc-design

Star

Workspace for CSE4178 - Basic SoC Design course (기초SOC설계), Fall 2020, Sogang University

magic vhdl spice verilog vivado sogang hdl soc soc-design cse4178

Updated Dec 18, 2020
Tcl

Adarsh-Kumar-Nayak / RISC-V-single-cycle-processor-Sum-of-n-numbers

Star

This project provides an insight into the internal verification of a 32-bit single cycle processor that implements the Reduced Instruction Set-V and displayed on seven segment on Basys3 FPGA board. The hardware structures were realized using Verilog Hardware Description Language.

processor-architecture fpga processor verilog instruction-set-architecture risc-v fpga-board 7-segment-display risc-v-architecture

Updated Dec 7, 2022
Tcl

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verilog

Here are 67 public repositories matching this topic...

pavel-demin / red-pitaya-notes

d953i / Custom_Part_Data_Files

kkiningh / cs231n-project

Essenceia / ethernet-physical-layer

stineje / sky130_cds

icglue / icglue

LSC-Unicamp / processor-ci-controller

Choaib-ELMADI / fpga-programming-for-beginners

kkiningh / synthesis-example

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

timothystotts / fpga-serial-acl-tester-3

yunusesergun / yesergun.fpga.dev

avinashy2j / StaticTimingAnalysis

suoglu / Divider

RomeoMe5 / FPGA-Matrix-Base-operations

marplyn / Processor-Systems-Architecture

Unicamp-Odhin / PDM_Microphone

Bucknalla / warc_fusesoc

hummingbird-12 / soc-design

Adarsh-Kumar-Nayak / RISC-V-single-cycle-processor-Sum-of-n-numbers

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