[WIP] Dockerize Synopsys/Cadence EDA tools
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Mar 29, 2019 - Dockerfile
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synopsys
Here are 39 public repositories matching this topic...
embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC
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Apr 25, 2024 - C
This is a tutorial on standard digital design flow
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May 24, 2021 - Tcl
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
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Sep 8, 2024 - Verilog
A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.
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Mar 25, 2023 - Jupyter Notebook
Technology file parser in Rust
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Apr 6, 2021 - Rust
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
script optimization polito tcl project synopsys dvs primetime voltage-scaling design-vision synopsys-dc
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Jun 9, 2021 - Verilog
Example of a full DC synthesis script for a simple design
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Feb 25, 2019 - Tcl
🌟 Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown
computer-science education google internship skills curriculum-vitae taiwan competitive-programming programming-contests taipei synopsys
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May 23, 2018 - CSS
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
optimization polito microprocessor synthesis synopsys dlx cadence digital-design physical-design dlx-microprocessor
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Jun 9, 2021 - Verilog
Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.
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Mar 1, 2025 - Java
Typical project for Synopsys DC Compiler
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Jun 21, 2018 - Tcl
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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May 12, 2024 - SystemVerilog
I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.
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Oct 24, 2024 - Verilog
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