rv32i: force semihosting insn sequence to be contained in single page #3364
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As specified in the RISC-V Semihosting discussion document[1], the
semihosting instruction sequence must be fully contained in a single
memory page. This can be accomplished through 16-byte alignment of the
instruction sequence. However, in contrast to the trap function
example provided in the document, we need to perform the aligment
before setting `norvc`. The preceding instruction may have been a
compressed instruction and ended on a 2-byte boundary. In this case, a
compressed nop instruction needs to be used to restore proper
alignment, which would be forbidden by the use of `norvc`, generating
an error such as the following:
LLVM ERROR: unable to write nop sequence of 2 bytes
[1]: https://github.com/riscv-software-src/riscv-semihosting/blob/f2e0eaf46d34a54ebbc1799c9a8879c4cc544fe4/riscv-semihosting-spec.adoc
hudson-ayers
approved these changes
Jan 2, 2023
twilfredo
approved these changes
Jan 4, 2023
alistair23
approved these changes
Jan 6, 2023
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bors r+ |
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Pull Request Overview
As specified in the RISC-V Semihosting discussion document1, the semihosting instruction sequence must be fully contained in a single memory page. This can be accomplished through 16-byte alignment of the instruction sequence. However, in contrast to the trap function example provided in the document, we need to perform the aligment before setting
norvc. The preceding instruction may have been a compressed instruction and ended on a 2-byte boundary. In this case, a compressed nop instruction needs to be used to restore proper alignment, which would be forbidden by the use ofnorvc, generating an error such as the following:Testing Strategy
This pull request was tested by running it with the QEMU RISC-V 32-bit
virttarget and forcing a panic.TODO or Help Wanted
N/A
Documentation Updated
Updated the relevant files inor no updates are required./docs,Formatting
make prepush.