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Starred repositories
Harvard University's CS50AI - Introduction to AI
Tools for working with circuits as graphs in python
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Lark is a parsing toolkit for Python, built with a focus on ergonomics, performance and modularity.
An open-source, customizable intermediate logic textbook
An Open-Source Design and Verification Environment for RISC-V
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
PQR5ASM is a RISC-V Assembler compliant with RV32I
Package manager and build abstraction tool for FPGA/ASIC development
This repository is for (pre-)release versions of the Revolution EDA.
Apply LLMs to your data, build personal assistants, and expand your use of LLMs with agents, chains, and memories.
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
RISC-V Formal Verification Framework
A rudimental RISCV CPU supporting RV32I instructions, in VHDL
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.